[FIRRTL] Expose an option to disable RAUW/replaceUsesWithIf in LowerLayers/LowerXMR to preserve RTL readability

[unlsycn]

Recent PRs #9654 and #9657 introduced a fallback mechanism to support XMRs/Probes on targets like module ports (BlockArgument) by creating a NodeOp (_probe) and replacing subsequent uses via replaceUsesWithIf or replaceAllUsesExcept.

While this correctly addresses the "uncovered dead wire" issue in certain vendor formal tools, it significantly degrades RTL readability for users who do not rely on those tools. For example, a simple passthrough assign output_0 = input_0; now becomes assign output_0 = input_0_probe;.

Could we expose a compiler option (e.g., --preserve-values-with-probes or --disable-probe-rauw in firtool) to toggle this RAUW behavior?

Ideally:

• Default: Keep the current RAUW behavior for formal tool compatibility.
• Opt-out: Generate the NodeOp for the XMR but skip the replaceUsesWithIf step, preserving the original signal as the driver for the rest of the circuit.

[unlsycn]

cc @seldridge

[seldridge]

Sorry about this, @unlsycn!

What I'd prefer is if the node can be elided in the situation you're talking about. This was _one_situation that I didn't properly inline (port being probed). The other was an expression being probed (and expressions can't handle symbols).

Would improving the inlining here, e.g., putting the probe on input_0 or output_0 work?

[unlsycn]

Yes, that approach works fine for us. Since my main concern is strictly RTL readability and avoiding unnecessary indirection, eliding the node for probed ports is a great solution.

Here is the previous Verilog output:

module Foo(
  input  [31:0] input_0,
                input_1,
  output [31:0] output_0,
                output_1
);

  wire [31:0] input_1_probe = input_1;
  wire [31:0] input_0_probe = input_0;
  assign output_0 = input_0;
  assign output_1 = input_1;
endmodule

`define ref_Foo_probe_0 input_0_probe
`define ref_Foo_probe_1 input_1_probe

Here is what we are currently seeing:

module Foo(
  input  [31:0] input_0,
                input_1,
  output [31:0] output_0,
                output_1
);

  wire [31:0] input_1_probe = input_1;
  wire [31:0] input_0_probe = input_0;
  assign output_0 = input_0_probe;
  assign output_1 = input_1_probe;
endmodule

`define ref_Foo_probe_0 input_0_probe
`define ref_Foo_probe_1 input_1_probe

And here is the output we'd expect and happily accept:

module Foo(
  input  [31:0] input_0,
                input_1,
  output [31:0] output_0,
                output_1
);

  assign output_0 = input_0;
  assign output_1 = input_1;
endmodule

`define ref_Foo_probe_0 input_0
`define ref_Foo_probe_1 input_1