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davemgreendavemgreen
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[DAG][AArch64] Handle truncated buildvectors to allow and(subvector(anyext)) fold.
This fold was not handling the extended BUILDVECTORs that we see when i8/i16 are not legal types. Using isConstOrConstSplat(N1, false, true) allows it to match truncated constants. The other changes are to make sure that truncated values in N1C are treated correctly, the fold we are mostly interested in is ``` if (N0.getOpcode() == ISD::EXTRACT_SUBVECTOR && N0.hasOneUse() && N1C && ISD::isExtOpcode(N0.getOperand(0).getOpcode())) { ```
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7 files changed

+60
-112
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7 files changed

+60
-112
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Diff for: ‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

+3-2
Original file line numberDiff line numberDiff line change
@@ -7166,7 +7166,7 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
71667166

71677167
// if (and x, c) is known to be zero, return 0
71687168
unsigned BitWidth = VT.getScalarSizeInBits();
7169-
ConstantSDNode *N1C = isConstOrConstSplat(N1);
7169+
ConstantSDNode *N1C = isConstOrConstSplat(N1, false, true);
71707170
if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), APInt::getAllOnes(BitWidth)))
71717171
return DAG.getConstant(0, DL, VT);
71727172

@@ -7205,7 +7205,8 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
72057205
return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0Op0);
72067206

72077207
// fold (and (any_ext V), c) -> (zero_ext (and (trunc V), c)) if profitable.
7208-
if (N1C->getAPIntValue().countLeadingZeros() >= (BitWidth - SrcBitWidth) &&
7208+
APInt N1APInt = N1C->getAPIntValue().trunc(VT.getScalarSizeInBits());
7209+
if (N1APInt.countLeadingZeros() >= (BitWidth - SrcBitWidth) &&
72097210
TLI.isTruncateFree(VT, SrcVT) && TLI.isZExtFree(SrcVT, VT) &&
72107211
TLI.isTypeDesirableForOp(ISD::AND, SrcVT) &&
72117212
TLI.isNarrowingProfitable(N, VT, SrcVT))

Diff for: ‎llvm/test/CodeGen/AArch64/aarch64-neon-vector-insert-uaddlv.ll

+4-8
Original file line numberDiff line numberDiff line change
@@ -282,8 +282,7 @@ define void @insert_vec_v16i8_uaddlv_from_v8i8(ptr %0) {
282282
; CHECK-NEXT: uaddlv.8b h1, v0
283283
; CHECK-NEXT: stp q0, q0, [x0, #32]
284284
; CHECK-NEXT: mov.b v2[0], v1[0]
285-
; CHECK-NEXT: zip1.8b v2, v2, v2
286-
; CHECK-NEXT: bic.4h v2, #255, lsl #8
285+
; CHECK-NEXT: ushll.8h v2, v2, #0
287286
; CHECK-NEXT: ushll.4s v2, v2, #0
288287
; CHECK-NEXT: ucvtf.4s v2, v2
289288
; CHECK-NEXT: stp q2, q0, [x0]
@@ -305,8 +304,7 @@ define void @insert_vec_v8i8_uaddlv_from_v8i8(ptr %0) {
305304
; CHECK-NEXT: stp xzr, xzr, [x0, #16]
306305
; CHECK-NEXT: uaddlv.8b h1, v0
307306
; CHECK-NEXT: mov.b v0[0], v1[0]
308-
; CHECK-NEXT: zip1.8b v0, v0, v0
309-
; CHECK-NEXT: bic.4h v0, #255, lsl #8
307+
; CHECK-NEXT: ushll.8h v0, v0, #0
310308
; CHECK-NEXT: ushll.4s v0, v0, #0
311309
; CHECK-NEXT: ucvtf.4s v0, v0
312310
; CHECK-NEXT: str q0, [x0]
@@ -436,8 +434,7 @@ define void @insert_vec_v8i8_uaddlv_from_v4i32(ptr %0) {
436434
; CHECK-NEXT: stp xzr, xzr, [x0, #16]
437435
; CHECK-NEXT: uaddlv.4s d0, v0
438436
; CHECK-NEXT: mov.b v1[0], v0[0]
439-
; CHECK-NEXT: zip1.8b v1, v1, v1
440-
; CHECK-NEXT: bic.4h v1, #255, lsl #8
437+
; CHECK-NEXT: ushll.8h v1, v1, #0
441438
; CHECK-NEXT: ushll.4s v1, v1, #0
442439
; CHECK-NEXT: ucvtf.4s v1, v1
443440
; CHECK-NEXT: str q1, [x0]
@@ -461,8 +458,7 @@ define void @insert_vec_v16i8_uaddlv_from_v4i32(ptr %0) {
461458
; CHECK-NEXT: uaddlv.4s d0, v0
462459
; CHECK-NEXT: stp q2, q2, [x0, #32]
463460
; CHECK-NEXT: mov.b v1[0], v0[0]
464-
; CHECK-NEXT: zip1.8b v1, v1, v1
465-
; CHECK-NEXT: bic.4h v1, #255, lsl #8
461+
; CHECK-NEXT: ushll.8h v1, v1, #0
466462
; CHECK-NEXT: ushll.4s v1, v1, #0
467463
; CHECK-NEXT: ucvtf.4s v1, v1
468464
; CHECK-NEXT: stp q1, q2, [x0]

Diff for: ‎llvm/test/CodeGen/AArch64/ctlz.ll

+1-2
Original file line numberDiff line numberDiff line change
@@ -44,8 +44,7 @@ define void @v3i8(ptr %p1) {
4444
; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
4545
; CHECK-SD-NEXT: ldr s1, [x0]
4646
; CHECK-SD-NEXT: movi v0.4h, #8
47-
; CHECK-SD-NEXT: zip1 v1.8b, v1.8b, v1.8b
48-
; CHECK-SD-NEXT: bic v1.4h, #255, lsl #8
47+
; CHECK-SD-NEXT: ushll v1.8h, v1.8b, #0
4948
; CHECK-SD-NEXT: clz v1.4h, v1.4h
5049
; CHECK-SD-NEXT: sub v0.4h, v1.4h, v0.4h
5150
; CHECK-SD-NEXT: uzp1 v1.8b, v0.8b, v0.8b

Diff for: ‎llvm/test/CodeGen/AArch64/ctpop.ll

+1-2
Original file line numberDiff line numberDiff line change
@@ -43,8 +43,7 @@ define void @v3i8(ptr %p1) {
4343
; CHECK-SD-NEXT: sub sp, sp, #16
4444
; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
4545
; CHECK-SD-NEXT: ldr s0, [x0]
46-
; CHECK-SD-NEXT: zip1 v0.8b, v0.8b, v0.8b
47-
; CHECK-SD-NEXT: bic v0.4h, #255, lsl #8
46+
; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0
4847
; CHECK-SD-NEXT: cnt v0.8b, v0.8b
4948
; CHECK-SD-NEXT: uaddlp v0.4h, v0.8b
5049
; CHECK-SD-NEXT: uzp1 v1.8b, v0.8b, v0.8b

Diff for: ‎llvm/test/CodeGen/AArch64/itofp.ll

+31-59
Original file line numberDiff line numberDiff line change
@@ -5503,14 +5503,10 @@ define <8 x float> @utofp_v8i8_v8f32(<8 x i8> %a) {
55035503
; CHECK-SD-LABEL: utofp_v8i8_v8f32:
55045504
; CHECK-SD: // %bb.0: // %entry
55055505
; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0
5506-
; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
5507-
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
5508-
; CHECK-SD-NEXT: bic v0.4h, #255, lsl #8
5509-
; CHECK-SD-NEXT: bic v1.4h, #255, lsl #8
5506+
; CHECK-SD-NEXT: ushll2 v1.4s, v0.8h, #0
55105507
; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0
5511-
; CHECK-SD-NEXT: ushll v1.4s, v1.4h, #0
5512-
; CHECK-SD-NEXT: ucvtf v0.4s, v0.4s
55135508
; CHECK-SD-NEXT: ucvtf v1.4s, v1.4s
5509+
; CHECK-SD-NEXT: ucvtf v0.4s, v0.4s
55145510
; CHECK-SD-NEXT: ret
55155511
;
55165512
; CHECK-GI-LABEL: utofp_v8i8_v8f32:
@@ -5562,24 +5558,16 @@ entry:
55625558
define <16 x float> @utofp_v16i8_v16f32(<16 x i8> %a) {
55635559
; CHECK-SD-LABEL: utofp_v16i8_v16f32:
55645560
; CHECK-SD: // %bb.0: // %entry
5565-
; CHECK-SD-NEXT: ushll2 v1.8h, v0.16b, #0
5566-
; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0
5567-
; CHECK-SD-NEXT: ext v2.16b, v1.16b, v1.16b, #8
5568-
; CHECK-SD-NEXT: ext v3.16b, v0.16b, v0.16b, #8
5569-
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
5570-
; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
5571-
; CHECK-SD-NEXT: bic v0.4h, #255, lsl #8
5572-
; CHECK-SD-NEXT: bic v1.4h, #255, lsl #8
5573-
; CHECK-SD-NEXT: bic v2.4h, #255, lsl #8
5574-
; CHECK-SD-NEXT: bic v3.4h, #255, lsl #8
5575-
; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0
5576-
; CHECK-SD-NEXT: ushll v1.4s, v1.4h, #0
5577-
; CHECK-SD-NEXT: ushll v4.4s, v2.4h, #0
5578-
; CHECK-SD-NEXT: ushll v5.4s, v3.4h, #0
5579-
; CHECK-SD-NEXT: ucvtf v0.4s, v0.4s
5580-
; CHECK-SD-NEXT: ucvtf v2.4s, v1.4s
5581-
; CHECK-SD-NEXT: ucvtf v3.4s, v4.4s
5582-
; CHECK-SD-NEXT: ucvtf v1.4s, v5.4s
5561+
; CHECK-SD-NEXT: ushll v1.8h, v0.8b, #0
5562+
; CHECK-SD-NEXT: ushll2 v0.8h, v0.16b, #0
5563+
; CHECK-SD-NEXT: ushll v2.4s, v1.4h, #0
5564+
; CHECK-SD-NEXT: ushll2 v3.4s, v0.8h, #0
5565+
; CHECK-SD-NEXT: ushll2 v1.4s, v1.8h, #0
5566+
; CHECK-SD-NEXT: ushll v4.4s, v0.4h, #0
5567+
; CHECK-SD-NEXT: ucvtf v0.4s, v2.4s
5568+
; CHECK-SD-NEXT: ucvtf v3.4s, v3.4s
5569+
; CHECK-SD-NEXT: ucvtf v1.4s, v1.4s
5570+
; CHECK-SD-NEXT: ucvtf v2.4s, v4.4s
55835571
; CHECK-SD-NEXT: ret
55845572
;
55855573
; CHECK-GI-LABEL: utofp_v16i8_v16f32:
@@ -5656,42 +5644,26 @@ entry:
56565644
define <32 x float> @utofp_v32i8_v32f32(<32 x i8> %a) {
56575645
; CHECK-SD-LABEL: utofp_v32i8_v32f32:
56585646
; CHECK-SD: // %bb.0: // %entry
5659-
; CHECK-SD-NEXT: ushll2 v2.8h, v0.16b, #0
5660-
; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0
5661-
; CHECK-SD-NEXT: ushll2 v3.8h, v1.16b, #0
5662-
; CHECK-SD-NEXT: ushll v1.8h, v1.8b, #0
5663-
; CHECK-SD-NEXT: ext v4.16b, v2.16b, v2.16b, #8
5664-
; CHECK-SD-NEXT: ext v5.16b, v0.16b, v0.16b, #8
5665-
; CHECK-SD-NEXT: ext v6.16b, v3.16b, v3.16b, #8
5666-
; CHECK-SD-NEXT: ext v7.16b, v1.16b, v1.16b, #8
5667-
; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
5668-
; CHECK-SD-NEXT: // kill: def $d3 killed $d3 killed $q3
5669-
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
5670-
; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
5671-
; CHECK-SD-NEXT: bic v2.4h, #255, lsl #8
5672-
; CHECK-SD-NEXT: bic v0.4h, #255, lsl #8
5673-
; CHECK-SD-NEXT: bic v1.4h, #255, lsl #8
5674-
; CHECK-SD-NEXT: bic v3.4h, #255, lsl #8
5675-
; CHECK-SD-NEXT: bic v4.4h, #255, lsl #8
5676-
; CHECK-SD-NEXT: bic v5.4h, #255, lsl #8
5677-
; CHECK-SD-NEXT: bic v6.4h, #255, lsl #8
5678-
; CHECK-SD-NEXT: bic v7.4h, #255, lsl #8
5647+
; CHECK-SD-NEXT: ushll v2.8h, v0.8b, #0
5648+
; CHECK-SD-NEXT: ushll2 v0.8h, v0.16b, #0
5649+
; CHECK-SD-NEXT: ushll v3.8h, v1.8b, #0
5650+
; CHECK-SD-NEXT: ushll2 v1.8h, v1.16b, #0
5651+
; CHECK-SD-NEXT: ushll2 v4.4s, v2.8h, #0
56795652
; CHECK-SD-NEXT: ushll v2.4s, v2.4h, #0
5680-
; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0
5681-
; CHECK-SD-NEXT: ushll v1.4s, v1.4h, #0
5682-
; CHECK-SD-NEXT: ushll v17.4s, v3.4h, #0
5683-
; CHECK-SD-NEXT: ushll v16.4s, v4.4h, #0
5684-
; CHECK-SD-NEXT: ushll v5.4s, v5.4h, #0
5685-
; CHECK-SD-NEXT: ushll v18.4s, v6.4h, #0
5686-
; CHECK-SD-NEXT: ushll v19.4s, v7.4h, #0
5687-
; CHECK-SD-NEXT: ucvtf v2.4s, v2.4s
5688-
; CHECK-SD-NEXT: ucvtf v0.4s, v0.4s
5689-
; CHECK-SD-NEXT: ucvtf v4.4s, v1.4s
5690-
; CHECK-SD-NEXT: ucvtf v6.4s, v17.4s
5691-
; CHECK-SD-NEXT: ucvtf v3.4s, v16.4s
5692-
; CHECK-SD-NEXT: ucvtf v1.4s, v5.4s
5693-
; CHECK-SD-NEXT: ucvtf v7.4s, v18.4s
5694-
; CHECK-SD-NEXT: ucvtf v5.4s, v19.4s
5653+
; CHECK-SD-NEXT: ushll2 v5.4s, v0.8h, #0
5654+
; CHECK-SD-NEXT: ushll v6.4s, v0.4h, #0
5655+
; CHECK-SD-NEXT: ushll v7.4s, v3.4h, #0
5656+
; CHECK-SD-NEXT: ushll2 v16.4s, v1.8h, #0
5657+
; CHECK-SD-NEXT: ushll2 v17.4s, v3.8h, #0
5658+
; CHECK-SD-NEXT: ushll v18.4s, v1.4h, #0
5659+
; CHECK-SD-NEXT: ucvtf v1.4s, v4.4s
5660+
; CHECK-SD-NEXT: ucvtf v0.4s, v2.4s
5661+
; CHECK-SD-NEXT: ucvtf v3.4s, v5.4s
5662+
; CHECK-SD-NEXT: ucvtf v2.4s, v6.4s
5663+
; CHECK-SD-NEXT: ucvtf v4.4s, v7.4s
5664+
; CHECK-SD-NEXT: ucvtf v7.4s, v16.4s
5665+
; CHECK-SD-NEXT: ucvtf v5.4s, v17.4s
5666+
; CHECK-SD-NEXT: ucvtf v6.4s, v18.4s
56955667
; CHECK-SD-NEXT: ret
56965668
;
56975669
; CHECK-GI-LABEL: utofp_v32i8_v32f32:

Diff for: ‎llvm/test/CodeGen/AArch64/vec3-loads-ext-trunc-stores.ll

+8-15
Original file line numberDiff line numberDiff line change
@@ -444,8 +444,7 @@ define void @load_ext_to_64bits(ptr %src, ptr %dst) {
444444
; CHECK-NEXT: orr w8, w9, w8, lsl #16
445445
; CHECK-NEXT: fmov s0, w8
446446
; CHECK-NEXT: add x8, x1, #4
447-
; CHECK-NEXT: zip1.8b v0, v0, v0
448-
; CHECK-NEXT: bic.4h v0, #255, lsl #8
447+
; CHECK-NEXT: ushll.8h v0, v0, #0
449448
; CHECK-NEXT: st1.h { v0 }[2], [x8]
450449
; CHECK-NEXT: str s0, [x1]
451450
; CHECK-NEXT: ret
@@ -480,8 +479,7 @@ define void @load_ext_to_64bits_default_align(ptr %src, ptr %dst) {
480479
; CHECK: ; %bb.0: ; %entry
481480
; CHECK-NEXT: ldr s0, [x0]
482481
; CHECK-NEXT: add x8, x1, #4
483-
; CHECK-NEXT: zip1.8b v0, v0, v0
484-
; CHECK-NEXT: bic.4h v0, #255, lsl #8
482+
; CHECK-NEXT: ushll.8h v0, v0, #0
485483
; CHECK-NEXT: st1.h { v0 }[2], [x8]
486484
; CHECK-NEXT: str s0, [x1]
487485
; CHECK-NEXT: ret
@@ -491,8 +489,7 @@ define void @load_ext_to_64bits_default_align(ptr %src, ptr %dst) {
491489
; BE-NEXT: ldr s0, [x0]
492490
; BE-NEXT: add x8, x1, #4
493491
; BE-NEXT: rev32 v0.8b, v0.8b
494-
; BE-NEXT: zip1 v0.8b, v0.8b, v0.8b
495-
; BE-NEXT: bic v0.4h, #255, lsl #8
492+
; BE-NEXT: ushll v0.8h, v0.8b, #0
496493
; BE-NEXT: rev32 v1.8h, v0.8h
497494
; BE-NEXT: st1 { v0.h }[2], [x8]
498495
; BE-NEXT: str s1, [x1]
@@ -509,8 +506,7 @@ define void @load_ext_to_64bits_align_4(ptr %src, ptr %dst) {
509506
; CHECK: ; %bb.0: ; %entry
510507
; CHECK-NEXT: ldr s0, [x0]
511508
; CHECK-NEXT: add x8, x1, #4
512-
; CHECK-NEXT: zip1.8b v0, v0, v0
513-
; CHECK-NEXT: bic.4h v0, #255, lsl #8
509+
; CHECK-NEXT: ushll.8h v0, v0, #0
514510
; CHECK-NEXT: st1.h { v0 }[2], [x8]
515511
; CHECK-NEXT: str s0, [x1]
516512
; CHECK-NEXT: ret
@@ -520,8 +516,7 @@ define void @load_ext_to_64bits_align_4(ptr %src, ptr %dst) {
520516
; BE-NEXT: ldr s0, [x0]
521517
; BE-NEXT: add x8, x1, #4
522518
; BE-NEXT: rev32 v0.8b, v0.8b
523-
; BE-NEXT: zip1 v0.8b, v0.8b, v0.8b
524-
; BE-NEXT: bic v0.4h, #255, lsl #8
519+
; BE-NEXT: ushll v0.8h, v0.8b, #0
525520
; BE-NEXT: rev32 v1.8h, v0.8h
526521
; BE-NEXT: st1 { v0.h }[2], [x8]
527522
; BE-NEXT: str s1, [x1]
@@ -541,13 +536,11 @@ define void @load_ext_add_to_64bits(ptr %src, ptr %dst) {
541536
; CHECK-NEXT: Lloh2:
542537
; CHECK-NEXT: adrp x8, lCPI15_0@PAGE
543538
; CHECK-NEXT: Lloh3:
544-
; CHECK-NEXT: ldr d1, [x8, lCPI15_0@PAGEOFF]
539+
; CHECK-NEXT: ldr d0, [x8, lCPI15_0@PAGEOFF]
545540
; CHECK-NEXT: add x8, x1, #4
546541
; CHECK-NEXT: orr w9, w10, w9, lsl #16
547-
; CHECK-NEXT: fmov s0, w9
548-
; CHECK-NEXT: zip1.8b v0, v0, v0
549-
; CHECK-NEXT: bic.4h v0, #255, lsl #8
550-
; CHECK-NEXT: add.4h v0, v0, v1
542+
; CHECK-NEXT: fmov s1, w9
543+
; CHECK-NEXT: uaddw.8h v0, v0, v1
551544
; CHECK-NEXT: st1.h { v0 }[2], [x8]
552545
; CHECK-NEXT: str s0, [x1]
553546
; CHECK-NEXT: ret

Diff for: ‎llvm/test/CodeGen/AArch64/vector-fcvt.ll

+12-24
Original file line numberDiff line numberDiff line change
@@ -114,14 +114,10 @@ define <8 x float> @uitofp_v8i8_float(<8 x i8> %a) {
114114
; CHECK-LABEL: uitofp_v8i8_float:
115115
; CHECK: // %bb.0:
116116
; CHECK-NEXT: ushll v0.8h, v0.8b, #0
117-
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
118-
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
119-
; CHECK-NEXT: bic v0.4h, #255, lsl #8
120-
; CHECK-NEXT: bic v1.4h, #255, lsl #8
117+
; CHECK-NEXT: ushll2 v1.4s, v0.8h, #0
121118
; CHECK-NEXT: ushll v0.4s, v0.4h, #0
122-
; CHECK-NEXT: ushll v1.4s, v1.4h, #0
123-
; CHECK-NEXT: ucvtf v0.4s, v0.4s
124119
; CHECK-NEXT: ucvtf v1.4s, v1.4s
120+
; CHECK-NEXT: ucvtf v0.4s, v0.4s
125121
; CHECK-NEXT: ret
126122
%1 = uitofp <8 x i8> %a to <8 x float>
127123
ret <8 x float> %1
@@ -130,24 +126,16 @@ define <8 x float> @uitofp_v8i8_float(<8 x i8> %a) {
130126
define <16 x float> @uitofp_v16i8_float(<16 x i8> %a) {
131127
; CHECK-LABEL: uitofp_v16i8_float:
132128
; CHECK: // %bb.0:
133-
; CHECK-NEXT: ushll2 v1.8h, v0.16b, #0
134-
; CHECK-NEXT: ushll v0.8h, v0.8b, #0
135-
; CHECK-NEXT: ext v2.16b, v1.16b, v1.16b, #8
136-
; CHECK-NEXT: ext v3.16b, v0.16b, v0.16b, #8
137-
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
138-
; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q1
139-
; CHECK-NEXT: bic v0.4h, #255, lsl #8
140-
; CHECK-NEXT: bic v1.4h, #255, lsl #8
141-
; CHECK-NEXT: bic v2.4h, #255, lsl #8
142-
; CHECK-NEXT: bic v3.4h, #255, lsl #8
143-
; CHECK-NEXT: ushll v0.4s, v0.4h, #0
144-
; CHECK-NEXT: ushll v1.4s, v1.4h, #0
145-
; CHECK-NEXT: ushll v4.4s, v2.4h, #0
146-
; CHECK-NEXT: ushll v5.4s, v3.4h, #0
147-
; CHECK-NEXT: ucvtf v0.4s, v0.4s
148-
; CHECK-NEXT: ucvtf v2.4s, v1.4s
149-
; CHECK-NEXT: ucvtf v3.4s, v4.4s
150-
; CHECK-NEXT: ucvtf v1.4s, v5.4s
129+
; CHECK-NEXT: ushll v1.8h, v0.8b, #0
130+
; CHECK-NEXT: ushll2 v0.8h, v0.16b, #0
131+
; CHECK-NEXT: ushll v2.4s, v1.4h, #0
132+
; CHECK-NEXT: ushll2 v3.4s, v0.8h, #0
133+
; CHECK-NEXT: ushll2 v1.4s, v1.8h, #0
134+
; CHECK-NEXT: ushll v4.4s, v0.4h, #0
135+
; CHECK-NEXT: ucvtf v0.4s, v2.4s
136+
; CHECK-NEXT: ucvtf v3.4s, v3.4s
137+
; CHECK-NEXT: ucvtf v1.4s, v1.4s
138+
; CHECK-NEXT: ucvtf v2.4s, v4.4s
151139
; CHECK-NEXT: ret
152140
%1 = uitofp <16 x i8> %a to <16 x float>
153141
ret <16 x float> %1

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