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support ISD::AssertFPNoClass
1 parent 92938f4 commit 32f4676

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7 files changed

+29
-11
lines changed

7 files changed

+29
-11
lines changed

Diff for: llvm/include/llvm/CodeGen/ISDOpcodes.h

+6
Original file line numberDiff line numberDiff line change
@@ -67,6 +67,12 @@ enum NodeType {
6767
/// poisoned the assertion will not be true for that value.
6868
AssertAlign,
6969

70+
/// AssertNoFPClass - These nodes record if a register contains a float
71+
/// value that is known to be not some type.
72+
/// NOTE: In case of the source value (or any vector element value) is
73+
/// poisoned the assertion will not be true for that value.
74+
AssertNoFPClass,
75+
7076
/// Various leaf nodes.
7177
BasicBlock,
7278
VALUETYPE,

Diff for: llvm/include/llvm/Target/TargetSelectionDAG.td

+1
Original file line numberDiff line numberDiff line change
@@ -859,6 +859,7 @@ def SDT_assert : SDTypeProfile<1, 1,
859859
[SDTCisInt<0>, SDTCisInt<1>, SDTCisSameAs<1, 0>]>;
860860
def assertsext : SDNode<"ISD::AssertSext", SDT_assert>;
861861
def assertzext : SDNode<"ISD::AssertZext", SDT_assert>;
862+
def assernofpclass : SDNode<"ISD::AssertNoFPClass", SDTFPUnaryOp>;
862863
def assertalign : SDNode<"ISD::AssertAlign", SDT_assert>;
863864

864865
def convergencectrl_anchor : SDNode<"ISD::CONVERGENCECTRL_ANCHOR",

Diff for: llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

+3
Original file line numberDiff line numberDiff line change
@@ -128,6 +128,7 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
128128
case ISD::UINT_TO_FP:
129129
case ISD::ZERO_EXTEND:
130130
case ISD::FCANONICALIZE:
131+
case ISD::AssertNoFPClass:
131132
R = ScalarizeVecRes_UnaryOp(N);
132133
break;
133134
case ISD::ADDRSPACECAST:
@@ -1276,6 +1277,7 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
12761277
case ISD::UINT_TO_FP:
12771278
case ISD::VP_UINT_TO_FP:
12781279
case ISD::FCANONICALIZE:
1280+
case ISD::AssertNoFPClass:
12791281
SplitVecRes_UnaryOp(N, Lo, Hi);
12801282
break;
12811283
case ISD::ADDRSPACECAST:
@@ -4843,6 +4845,7 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
48434845
case ISD::FREEZE:
48444846
case ISD::ARITH_FENCE:
48454847
case ISD::FCANONICALIZE:
4848+
case ISD::AssertNoFPClass:
48464849
Res = WidenVecRes_Unary(N);
48474850
break;
48484851
case ISD::FMA: case ISD::VP_FMA:

Diff for: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

+4
Original file line numberDiff line numberDiff line change
@@ -7384,6 +7384,10 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
73847384
N2.getOpcode() == ISD::TargetConstant && "Invalid FP_ROUND!");
73857385
if (N1.getValueType() == VT) return N1; // noop conversion.
73867386
break;
7387+
case ISD::AssertNoFPClass:
7388+
assert(N1.getValueType().isFloatingPoint() &&
7389+
"AssertNoFPClass is used for a non-floating type");
7390+
return N1;
73877391
case ISD::AssertSext:
73887392
case ISD::AssertZext: {
73897393
EVT EVT = cast<VTSDNode>(N2)->getVT();

Diff for: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

+13-11
Original file line numberDiff line numberDiff line change
@@ -11891,20 +11891,22 @@ void SelectionDAGISel::LowerArguments(const Function &F) {
1189111891
AssertOp = ISD::AssertSext;
1189211892
else if (Arg.hasAttribute(Attribute::ZExt))
1189311893
AssertOp = ISD::AssertZext;
11894-
if (Arg.hasAttribute(Attribute::NoFPClass)) {
11895-
SDNodeFlags InValFlags = InVals[i]->getFlags();
11894+
SDValue OutVal =
11895+
getCopyFromParts(DAG, dl, &InVals[i], NumParts, PartVT, VT, nullptr,
11896+
NewRoot, F.getCallingConv(), AssertOp);
11897+
if (Arg.hasAttribute(Attribute::NoFPClass) &&
11898+
OutVal.getValueType().isFloatingPoint()) {
11899+
SDNodeFlags OutValFlags = OutVal->getFlags();
1189611900
bool NoSNaN = ((Arg.getNoFPClass() & llvm::fcSNan) == llvm::fcSNan);
1189711901
bool NoQNaN = ((Arg.getNoFPClass() & llvm::fcQNan) == llvm::fcQNan);
11898-
InValFlags.setNoSNaNs(NoSNaN);
11899-
InValFlags.setNoQNaNs(NoQNaN);
11900-
InValFlags.setNoInfs((Arg.getNoFPClass() & llvm::fcInf) ==
11901-
llvm::fcInf);
11902-
InVals[i]->setFlags(InValFlags);
11902+
bool NoInf = ((Arg.getNoFPClass() & llvm::fcInf) == llvm::fcInf);
11903+
OutValFlags.setNoSNaNs(NoSNaN);
11904+
OutValFlags.setNoQNaNs(NoQNaN);
11905+
OutValFlags.setNoInfs(NoInf);
11906+
OutVal =
11907+
DAG.getNode(ISD::AssertNoFPClass, dl, VT, OutVal, OutValFlags);
1190311908
}
11904-
11905-
ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], NumParts,
11906-
PartVT, VT, nullptr, NewRoot,
11907-
F.getCallingConv(), AssertOp));
11909+
ArgValues.push_back(OutVal);
1190811910
}
1190911911

1191011912
i += NumParts;

Diff for: llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

+1
Original file line numberDiff line numberDiff line change
@@ -118,6 +118,7 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
118118
case ISD::TokenFactor: return "TokenFactor";
119119
case ISD::AssertSext: return "AssertSext";
120120
case ISD::AssertZext: return "AssertZext";
121+
case ISD::AssertNoFPClass: return "AssertNoFPClass";
121122
case ISD::AssertAlign: return "AssertAlign";
122123

123124
case ISD::BasicBlock: return "BasicBlock";

Diff for: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

+1
Original file line numberDiff line numberDiff line change
@@ -3262,6 +3262,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
32623262
return;
32633263
case ISD::AssertSext:
32643264
case ISD::AssertZext:
3265+
case ISD::AssertNoFPClass:
32653266
case ISD::AssertAlign:
32663267
ReplaceUses(SDValue(NodeToMatch, 0), NodeToMatch->getOperand(0));
32673268
CurDAG->RemoveDeadNode(NodeToMatch);

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