Skip to content

Commit 332f060

Browse files
ritter-x2aritter-x2a
authored
[SeparateConstOffsetFromGEP] Don't set unsound inbounds flag (#130616)
The language reference says about inbounds geps that "if the getelementptr has any non-zero indices[...] [t]he base pointer has an in bounds address of the allocated object that it is based on [and] [d]uring the successive addition of offsets to the address, the resulting pointer must remain in bounds of the allocated object at each step." If (gep inbounds p, (a + 5)) is translated to (gep [inbounds] (gep p, a), 5) with p pointing to the beginning of an object and a=-4, as the example in the comments suggests, that's the case for neither of the resulting geps. Therefore, we need to clear the inbounds flag for both geps. We might want to use ValueTracking to check if a is known to be non-negative to preserve the inbounds flags. For the AMDGPU tests with scratch instructions, removing the unsound inbounds flag means that AMDGPUDAGToDAGISel::isFlatScratchBaseLegal sees no NUW flag at the pointer add, which prevents generation of scratch instructions with immediate offsets. For SWDEV-516125.
1 parent 9cf46fb commit 332f060

15 files changed

+766
-305
lines changed

Diff for: ‎llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp

+3-3
Original file line numberDiff line numberDiff line change
@@ -1092,7 +1092,7 @@ bool SeparateConstOffsetFromGEP::splitGEP(GetElementPtrInst *GEP) {
10921092
// is transformed to:
10931093
//
10941094
// addr2 = gep float, float* p, i64 a ; inbounds removed
1095-
// addr = gep inbounds float, float* addr2, i64 5
1095+
// addr = gep float, float* addr2, i64 5 ; inbounds removed
10961096
//
10971097
// If a is -4, although the old index b is in bounds, the new index a is
10981098
// off-bound. http://llvm.org/docs/LangRef.html#id181 says "if the
@@ -1103,7 +1103,7 @@ bool SeparateConstOffsetFromGEP::splitGEP(GetElementPtrInst *GEP) {
11031103
// TODO(jingyue): do some range analysis to keep as many inbounds as
11041104
// possible. GEPs with inbounds are more friendly to alias analysis.
11051105
// TODO(gep_nowrap): Preserve nuw at least.
1106-
bool GEPWasInBounds = GEP->isInBounds();
1106+
GEPNoWrapFlags NewGEPFlags = GEPNoWrapFlags::none();
11071107
GEP->setNoWrapFlags(GEPNoWrapFlags::none());
11081108

11091109
// Lowers a GEP to either GEPs with a single index or arithmetic operations.
@@ -1153,7 +1153,7 @@ bool SeparateConstOffsetFromGEP::splitGEP(GetElementPtrInst *GEP) {
11531153
IRBuilder<> Builder(GEP);
11541154
NewGEP = cast<Instruction>(Builder.CreatePtrAdd(
11551155
NewGEP, ConstantInt::get(PtrIdxTy, AccumulativeByteOffset, true),
1156-
GEP->getName(), GEPWasInBounds));
1156+
GEP->getName(), NewGEPFlags));
11571157
NewGEP->copyMetadata(*GEP);
11581158

11591159
GEP->replaceAllUsesWith(NewGEP);

Diff for: ‎llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll

+264-100
Large diffs are not rendered by default.

Diff for: ‎llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll

+4-4
Original file line numberDiff line numberDiff line change
@@ -238,8 +238,8 @@ main_body:
238238
%25 = getelementptr inbounds [0 x <8 x i32>], ptr addrspace(6) %1, i32 0, i32 %24, !amdgpu.uniform !0
239239
%26 = load <8 x i32>, ptr addrspace(6) %25, align 32, !invariant.load !0
240240
%27 = shl i32 %23, 2
241-
%28 = or disjoint i32 %27, 3
242-
%29 = getelementptr inbounds [0 x <4 x i32>], ptr addrspace(6) %1, i32 0, i32 %28, !amdgpu.uniform !0
241+
%28 = getelementptr [0 x <4 x i32>], ptr addrspace(6) %1, i32 0, i32 %27, !amdgpu.uniform !0
242+
%29 = getelementptr inbounds [0 x <4 x i32>], ptr addrspace(6) %28, i32 0, i32 3, !amdgpu.uniform !0
243243
%30 = load <4 x i32>, ptr addrspace(6) %29, align 16, !invariant.load !0
244244
%31 = call nsz <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float 0.0, <8 x i32> %26, <4 x i32> %30, i1 0, i32 0, i32 0) #8
245245
%32 = extractelement <4 x float> %31, i32 0
@@ -270,8 +270,8 @@ main_body:
270270
%25 = getelementptr inbounds [0 x <8 x i32>], ptr addrspace(6) %1, i32 0, i32 %24
271271
%26 = load <8 x i32>, ptr addrspace(6) %25, align 32, !invariant.load !0
272272
%27 = shl i32 %23, 2
273-
%28 = or disjoint i32 %27, 3
274-
%29 = getelementptr inbounds [0 x <4 x i32>], ptr addrspace(6) %1, i32 0, i32 %28
273+
%28 = getelementptr [0 x <4 x i32>], ptr addrspace(6) %1, i32 0, i32 %27
274+
%29 = getelementptr inbounds [0 x <4 x i32>], ptr addrspace(6) %28, i32 0, i32 3
275275
%30 = load <4 x i32>, ptr addrspace(6) %29, align 16, !invariant.load !0
276276
%31 = call nsz <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float 0.0, <8 x i32> %26, <4 x i32> %30, i1 0, i32 0, i32 0) #8
277277
%32 = extractelement <4 x float> %31, i32 0

Diff for: ‎llvm/test/CodeGen/AMDGPU/flat-scratch.ll

+231-108
Large diffs are not rendered by default.

Diff for: ‎llvm/test/CodeGen/AMDGPU/fold-gep-offset.ll

+159
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,159 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
3+
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -mattr=-enable-flat-scratch < %s | FileCheck --check-prefixes=GFX90A,GFX90A-MUBUF %s
4+
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -mattr=+enable-flat-scratch < %s | FileCheck --check-prefixes=GFX90A,GFX90A-FLATSCR %s
5+
; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -mattr=-enable-flat-scratch < %s | FileCheck --check-prefixes=GFX10,GFX10-MUBUF %s
6+
; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -mattr=+enable-flat-scratch < %s | FileCheck --check-prefixes=GFX10,GFX10-FLATSCR %s
7+
; RUN: llc -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck --check-prefixes=GFX942 %s
8+
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck --check-prefixes=GFX11 %s
9+
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck --check-prefixes=GFX12 %s
10+
11+
; This test checks memory addresses with constant offset components that should
12+
; not be folded into memory accesses with immediate offsets.
13+
; SeparateConstOffsetsFromGEP transforms the GEPs in a way that can lead to
14+
; out-of-bounds or negative intermediate results in the address computation,
15+
; which are problematic for flat and scratch instructions:
16+
; gep[inbounds](p, i + 3) -> gep(gep(p, i), 3)
17+
18+
19+
; FIXME the offset here should not be folded: if %p points to the beginning of
20+
; scratch or LDS and %i is -1, a folded offset crashes the program.
21+
define i32 @flat_offset_maybe_oob(ptr %p, i32 %i) {
22+
; GFX90A-LABEL: flat_offset_maybe_oob:
23+
; GFX90A: ; %bb.0:
24+
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
25+
; GFX90A-NEXT: v_ashrrev_i32_e32 v3, 31, v2
26+
; GFX90A-NEXT: v_lshlrev_b64 v[2:3], 2, v[2:3]
27+
; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
28+
; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
29+
; GFX90A-NEXT: flat_load_dword v0, v[0:1] offset:12
30+
; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
31+
; GFX90A-NEXT: s_setpc_b64 s[30:31]
32+
;
33+
; GFX10-LABEL: flat_offset_maybe_oob:
34+
; GFX10: ; %bb.0:
35+
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
36+
; GFX10-NEXT: v_ashrrev_i32_e32 v3, 31, v2
37+
; GFX10-NEXT: v_lshlrev_b64 v[2:3], 2, v[2:3]
38+
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
39+
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
40+
; GFX10-NEXT: flat_load_dword v0, v[0:1] offset:12
41+
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
42+
; GFX10-NEXT: s_setpc_b64 s[30:31]
43+
;
44+
; GFX942-LABEL: flat_offset_maybe_oob:
45+
; GFX942: ; %bb.0:
46+
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
47+
; GFX942-NEXT: v_ashrrev_i32_e32 v3, 31, v2
48+
; GFX942-NEXT: v_lshl_add_u64 v[0:1], v[2:3], 2, v[0:1]
49+
; GFX942-NEXT: flat_load_dword v0, v[0:1] offset:12
50+
; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
51+
; GFX942-NEXT: s_setpc_b64 s[30:31]
52+
;
53+
; GFX11-LABEL: flat_offset_maybe_oob:
54+
; GFX11: ; %bb.0:
55+
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
56+
; GFX11-NEXT: v_ashrrev_i32_e32 v3, 31, v2
57+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
58+
; GFX11-NEXT: v_lshlrev_b64 v[2:3], 2, v[2:3]
59+
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
60+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
61+
; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
62+
; GFX11-NEXT: flat_load_b32 v0, v[0:1] offset:12
63+
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
64+
; GFX11-NEXT: s_setpc_b64 s[30:31]
65+
;
66+
; GFX12-LABEL: flat_offset_maybe_oob:
67+
; GFX12: ; %bb.0:
68+
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
69+
; GFX12-NEXT: s_wait_expcnt 0x0
70+
; GFX12-NEXT: s_wait_samplecnt 0x0
71+
; GFX12-NEXT: s_wait_bvhcnt 0x0
72+
; GFX12-NEXT: s_wait_kmcnt 0x0
73+
; GFX12-NEXT: v_ashrrev_i32_e32 v3, 31, v2
74+
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
75+
; GFX12-NEXT: v_lshlrev_b64_e32 v[2:3], 2, v[2:3]
76+
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
77+
; GFX12-NEXT: s_wait_alu 0xfffd
78+
; GFX12-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
79+
; GFX12-NEXT: flat_load_b32 v0, v[0:1] offset:12
80+
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
81+
; GFX12-NEXT: s_wait_alu 0xfffd
82+
; GFX12-NEXT: s_setpc_b64 s[30:31]
83+
%idx = add nsw i32 %i, 3
84+
%arrayidx = getelementptr inbounds i32, ptr %p, i32 %idx
85+
%l = load i32, ptr %arrayidx
86+
ret i32 %l
87+
}
88+
89+
; For MUBUF and for GFX12, folding the offset is okay.
90+
define i32 @private_offset_maybe_oob(ptr addrspace(5) %p, i32 %i) {
91+
; GFX90A-MUBUF-LABEL: private_offset_maybe_oob:
92+
; GFX90A-MUBUF: ; %bb.0:
93+
; GFX90A-MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
94+
; GFX90A-MUBUF-NEXT: v_lshl_add_u32 v0, v1, 2, v0
95+
; GFX90A-MUBUF-NEXT: buffer_load_dword v0, v0, s[0:3], 0 offen offset:12
96+
; GFX90A-MUBUF-NEXT: s_waitcnt vmcnt(0)
97+
; GFX90A-MUBUF-NEXT: s_setpc_b64 s[30:31]
98+
;
99+
; GFX90A-FLATSCR-LABEL: private_offset_maybe_oob:
100+
; GFX90A-FLATSCR: ; %bb.0:
101+
; GFX90A-FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
102+
; GFX90A-FLATSCR-NEXT: v_lshlrev_b32_e32 v1, 2, v1
103+
; GFX90A-FLATSCR-NEXT: v_add3_u32 v0, v0, v1, 12
104+
; GFX90A-FLATSCR-NEXT: scratch_load_dword v0, v0, off
105+
; GFX90A-FLATSCR-NEXT: s_waitcnt vmcnt(0)
106+
; GFX90A-FLATSCR-NEXT: s_setpc_b64 s[30:31]
107+
;
108+
; GFX10-MUBUF-LABEL: private_offset_maybe_oob:
109+
; GFX10-MUBUF: ; %bb.0:
110+
; GFX10-MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
111+
; GFX10-MUBUF-NEXT: v_lshl_add_u32 v0, v1, 2, v0
112+
; GFX10-MUBUF-NEXT: buffer_load_dword v0, v0, s[0:3], 0 offen offset:12
113+
; GFX10-MUBUF-NEXT: s_waitcnt vmcnt(0)
114+
; GFX10-MUBUF-NEXT: s_setpc_b64 s[30:31]
115+
;
116+
; GFX10-FLATSCR-LABEL: private_offset_maybe_oob:
117+
; GFX10-FLATSCR: ; %bb.0:
118+
; GFX10-FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
119+
; GFX10-FLATSCR-NEXT: v_lshlrev_b32_e32 v1, 2, v1
120+
; GFX10-FLATSCR-NEXT: v_add3_u32 v0, v0, v1, 12
121+
; GFX10-FLATSCR-NEXT: scratch_load_dword v0, v0, off
122+
; GFX10-FLATSCR-NEXT: s_waitcnt vmcnt(0)
123+
; GFX10-FLATSCR-NEXT: s_setpc_b64 s[30:31]
124+
;
125+
; GFX942-LABEL: private_offset_maybe_oob:
126+
; GFX942: ; %bb.0:
127+
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
128+
; GFX942-NEXT: v_lshlrev_b32_e32 v1, 2, v1
129+
; GFX942-NEXT: v_add3_u32 v0, v0, v1, 12
130+
; GFX942-NEXT: scratch_load_dword v0, v0, off
131+
; GFX942-NEXT: s_waitcnt vmcnt(0)
132+
; GFX942-NEXT: s_setpc_b64 s[30:31]
133+
;
134+
; GFX11-LABEL: private_offset_maybe_oob:
135+
; GFX11: ; %bb.0:
136+
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
137+
; GFX11-NEXT: v_lshlrev_b32_e32 v1, 2, v1
138+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
139+
; GFX11-NEXT: v_add3_u32 v0, v0, v1, 12
140+
; GFX11-NEXT: scratch_load_b32 v0, v0, off
141+
; GFX11-NEXT: s_waitcnt vmcnt(0)
142+
; GFX11-NEXT: s_setpc_b64 s[30:31]
143+
;
144+
; GFX12-LABEL: private_offset_maybe_oob:
145+
; GFX12: ; %bb.0:
146+
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
147+
; GFX12-NEXT: s_wait_expcnt 0x0
148+
; GFX12-NEXT: s_wait_samplecnt 0x0
149+
; GFX12-NEXT: s_wait_bvhcnt 0x0
150+
; GFX12-NEXT: s_wait_kmcnt 0x0
151+
; GFX12-NEXT: v_lshl_add_u32 v0, v1, 2, v0
152+
; GFX12-NEXT: scratch_load_b32 v0, v0, off offset:12
153+
; GFX12-NEXT: s_wait_loadcnt 0x0
154+
; GFX12-NEXT: s_setpc_b64 s[30:31]
155+
%idx = add nsw i32 %i, 3
156+
%arrayidx = getelementptr inbounds i32, ptr addrspace(5) %p, i32 %idx
157+
%l = load i32, ptr addrspace(5) %arrayidx
158+
ret i32 %l
159+
}

Diff for: ‎llvm/test/CodeGen/AMDGPU/memory_clause.ll

+10-13
Original file line numberDiff line numberDiff line change
@@ -225,22 +225,19 @@ define void @mubuf_clause(ptr addrspace(5) noalias nocapture readonly %arg, ptr
225225
; GCN-SCRATCH-NEXT: s_setpc_b64 s[30:31]
226226
bb:
227227
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
228-
%tmp2 = getelementptr inbounds <4 x i32>, ptr addrspace(5) %arg, i32 %tmp
229-
%tmp3 = load <4 x i32>, ptr addrspace(5) %tmp2, align 16
230-
%tmp4 = getelementptr inbounds <4 x i32>, ptr addrspace(5) %arg1, i32 %tmp
231-
%tmp5 = add nuw nsw i32 %tmp, 1
232-
%tmp6 = getelementptr inbounds <4 x i32>, ptr addrspace(5) %arg, i32 %tmp5
228+
%base = getelementptr inbounds <4 x i32>, ptr addrspace(5) %arg, i32 %tmp
229+
%tmp3 = load <4 x i32>, ptr addrspace(5) %base, align 16
230+
%base1 = getelementptr inbounds <4 x i32>, ptr addrspace(5) %arg1, i32 %tmp
231+
%tmp6 = getelementptr inbounds <4 x i32>, ptr addrspace(5) %base, i32 1
233232
%tmp7 = load <4 x i32>, ptr addrspace(5) %tmp6, align 16
234-
%tmp8 = getelementptr inbounds <4 x i32>, ptr addrspace(5) %arg1, i32 %tmp5
235-
%tmp9 = add nuw nsw i32 %tmp, 2
236-
%tmp10 = getelementptr inbounds <4 x i32>, ptr addrspace(5) %arg, i32 %tmp9
233+
%tmp8 = getelementptr inbounds <4 x i32>, ptr addrspace(5) %base1, i32 1
234+
%tmp10 = getelementptr inbounds <4 x i32>, ptr addrspace(5) %base, i32 2
237235
%tmp11 = load <4 x i32>, ptr addrspace(5) %tmp10, align 16
238-
%tmp12 = getelementptr inbounds <4 x i32>, ptr addrspace(5) %arg1, i32 %tmp9
239-
%tmp13 = add nuw nsw i32 %tmp, 3
240-
%tmp14 = getelementptr inbounds <4 x i32>, ptr addrspace(5) %arg, i32 %tmp13
236+
%tmp12 = getelementptr inbounds <4 x i32>, ptr addrspace(5) %base1, i32 2
237+
%tmp14 = getelementptr inbounds <4 x i32>, ptr addrspace(5) %base, i32 3
241238
%tmp15 = load <4 x i32>, ptr addrspace(5) %tmp14, align 16
242-
%tmp16 = getelementptr inbounds <4 x i32>, ptr addrspace(5) %arg1, i32 %tmp13
243-
store <4 x i32> %tmp3, ptr addrspace(5) %tmp4, align 16
239+
%tmp16 = getelementptr inbounds <4 x i32>, ptr addrspace(5) %base1, i32 3
240+
store <4 x i32> %tmp3, ptr addrspace(5) %base1, align 16
244241
store <4 x i32> %tmp7, ptr addrspace(5) %tmp8, align 16
245242
store <4 x i32> %tmp11, ptr addrspace(5) %tmp12, align 16
246243
store <4 x i32> %tmp15, ptr addrspace(5) %tmp16, align 16

Diff for: ‎llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/preserve-inbounds.ll

+18
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,18 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2+
; RUN: opt < %s -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -passes=separate-const-offset-from-gep -S | FileCheck %s
3+
4+
; The inbounds flags cannot be preserved here: If the pointers point to the
5+
; beginning of an object and %i is 1, the intermediate GEPs are out of bounds.
6+
define ptr @maybe_oob(ptr %p, i64 %i) {
7+
; CHECK-LABEL: @maybe_oob(
8+
; CHECK-NEXT: entry:
9+
; CHECK-NEXT: [[IDX1:%.*]] = sub i64 0, [[I:%.*]]
10+
; CHECK-NEXT: [[TMP0:%.*]] = getelementptr i32, ptr [[P:%.*]], i64 [[IDX1]]
11+
; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr i8, ptr [[TMP0]], i64 4
12+
; CHECK-NEXT: ret ptr [[ARRAYIDX2]]
13+
;
14+
entry:
15+
%idx = sub nsw i64 1, %i
16+
%arrayidx = getelementptr inbounds i32, ptr %p, i64 %idx
17+
ret ptr %arrayidx
18+
}

Diff for: ‎llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/split-gep-and-gvn-addrspace-addressing-modes.ll

+7-7
Original file line numberDiff line numberDiff line change
@@ -11,9 +11,9 @@ define amdgpu_kernel void @sum_of_array(i32 %x, i32 %y, ptr addrspace(1) nocaptu
1111
; IR-NEXT: [[TMP:%.*]] = sext i32 [[Y]] to i64
1212
; IR-NEXT: [[TMP1:%.*]] = sext i32 [[X]] to i64
1313
; IR-NEXT: [[TMP2:%.*]] = getelementptr [4096 x [32 x float]], ptr addrspace(4) @array, i64 0, i64 [[TMP1]], i64 [[TMP]]
14-
; IR-NEXT: [[TMP82:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[TMP2]], i64 4
15-
; IR-NEXT: [[TMP144:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[TMP2]], i64 128
16-
; IR-NEXT: [[TMP187:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[TMP2]], i64 132
14+
; IR-NEXT: [[TMP82:%.*]] = getelementptr i8, ptr addrspace(4) [[TMP2]], i64 4
15+
; IR-NEXT: [[TMP144:%.*]] = getelementptr i8, ptr addrspace(4) [[TMP2]], i64 128
16+
; IR-NEXT: [[TMP187:%.*]] = getelementptr i8, ptr addrspace(4) [[TMP2]], i64 132
1717
; IR-NEXT: store float 0.000000e+00, ptr addrspace(1) [[OUTPUT]], align 4
1818
; IR-NEXT: ret void
1919
;
@@ -51,7 +51,7 @@ define amdgpu_kernel void @sum_of_array_over_max_mubuf_offset(i32 %x, i32 %y, pt
5151
; IR-NEXT: [[TMP2:%.*]] = getelementptr [4096 x [4 x float]], ptr addrspace(4) @array2, i64 0, i64 [[TMP1]], i64 [[TMP]]
5252
; IR-NEXT: [[TMP6:%.*]] = add i32 [[Y]], 255
5353
; IR-NEXT: [[TMP7:%.*]] = sext i32 [[TMP6]] to i64
54-
; IR-NEXT: [[TMP82:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[TMP2]], i64 1020
54+
; IR-NEXT: [[TMP82:%.*]] = getelementptr i8, ptr addrspace(4) [[TMP2]], i64 1020
5555
; IR-NEXT: [[TMP12:%.*]] = add i32 [[X]], 256
5656
; IR-NEXT: [[TMP13:%.*]] = sext i32 [[TMP12]] to i64
5757
; IR-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4096 x [4 x float]], ptr addrspace(4) @array2, i64 0, i64 [[TMP13]], i64 [[TMP]]
@@ -91,13 +91,13 @@ define amdgpu_kernel void @sum_of_lds_array_over_max_mubuf_offset(i32 %x, i32 %y
9191
; IR-NEXT: [[TMP2:%.*]] = getelementptr [4096 x [4 x float]], ptr addrspace(3) @lds_array, i32 0, i32 [[X]], i32 [[Y]]
9292
; IR-NEXT: [[TMP4:%.*]] = load float, ptr addrspace(3) [[TMP2]], align 4
9393
; IR-NEXT: [[TMP5:%.*]] = fadd float [[TMP4]], 0.000000e+00
94-
; IR-NEXT: [[TMP82:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[TMP2]], i32 1020
94+
; IR-NEXT: [[TMP82:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP2]], i32 1020
9595
; IR-NEXT: [[TMP10:%.*]] = load float, ptr addrspace(3) [[TMP82]], align 4
9696
; IR-NEXT: [[TMP11:%.*]] = fadd float [[TMP5]], [[TMP10]]
97-
; IR-NEXT: [[TMP144:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[TMP2]], i32 64512
97+
; IR-NEXT: [[TMP144:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP2]], i32 64512
9898
; IR-NEXT: [[TMP16:%.*]] = load float, ptr addrspace(3) [[TMP144]], align 4
9999
; IR-NEXT: [[TMP17:%.*]] = fadd float [[TMP11]], [[TMP16]]
100-
; IR-NEXT: [[TMP187:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[TMP2]], i32 65532
100+
; IR-NEXT: [[TMP187:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP2]], i32 65532
101101
; IR-NEXT: [[TMP20:%.*]] = load float, ptr addrspace(3) [[TMP187]], align 4
102102
; IR-NEXT: [[TMP21:%.*]] = fadd float [[TMP17]], [[TMP20]]
103103
; IR-NEXT: store float [[TMP21]], ptr addrspace(1) [[OUTPUT]], align 4

0 commit comments

Comments
 (0)