Skip to content

Commit 4a991f3

Browse files
address review
1 parent 0c4b16a commit 4a991f3

File tree

1 file changed

+5
-9
lines changed

1 file changed

+5
-9
lines changed

Diff for: llvm/test/CodeGen/AMDGPU/fix-illegal-copy.ll

+5-9
Original file line numberDiff line numberDiff line change
@@ -1,17 +1,13 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
22
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 | FileCheck %s -check-prefixes=GFX11
33

4-
define amdgpu_ps i32 @s_copysign_uniform(float inreg %x, float inreg %y) {
5-
; GFX11-LABEL: s_copysign_uniform:
4+
define amdgpu_ps float @uniform_fpext(half inreg %x) {
5+
; GFX11-LABEL: uniform_fpext:
66
; GFX11: ; %bb.0:
7-
; GFX11-NEXT: v_mov_b32_e32 v0, s1
8-
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
9-
; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, s0, v0
10-
; GFX11-NEXT: v_readfirstlane_b32 s0, v0
7+
; GFX11-NEXT: v_cvt_f32_f16_e32 v0, s0
118
; GFX11-NEXT: ; return to shader part epilog
12-
%op = call float @llvm.copysign.f32(float %x, float %y)
13-
%cast = bitcast float %op to i32
14-
ret i32 %cast
9+
%f = fpext half %x to float
10+
ret float %f
1511
}
1612

1713
define amdgpu_ps i64 @uniform_vbfi_val_op(i32 inreg %a, i32 inreg %b) {

0 commit comments

Comments
 (0)