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gerekongerekon
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[Xtensa] Add fp16 conversion support
Close espressif#91
1 parent dd37265 commit 5e778ed

2 files changed

Lines changed: 175 additions & 0 deletions

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‎llvm/lib/Target/Xtensa/XtensaISelLowering.cpp‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -100,6 +100,11 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &TM,
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setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
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}
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setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
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setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
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setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
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setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
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setOperationAction(ISD::ConstantPool, PtrVT, Custom);
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setOperationAction(ISD::GlobalAddress, PtrVT, Custom);
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setOperationAction(ISD::GlobalTLSAddress, PtrVT, Custom);
@@ -244,8 +249,19 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::FP_TO_SINT, MVT::i32, Expand);
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}
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for (MVT VT : MVT::fp_valuetypes()) {
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setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
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}
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setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
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setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
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setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
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setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
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// Floating-point truncation and stores need to be done separately.
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setTruncStoreAction(MVT::f64, MVT::f32, Expand);
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setTruncStoreAction(MVT::f64, MVT::f16, Expand);
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setTruncStoreAction(MVT::f32, MVT::f16, Expand);
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if (Subtarget.hasS32C1I()) {
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setMaxAtomicSizeInBitsSupported(32);

‎llvm/test/CodeGen/Xtensa/fp16.ll‎

Lines changed: 159 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,159 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc -mtriple=xtensa -mcpu=esp32 < %s | FileCheck --check-prefix=CHECK-ESP32 %s
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; RUN: llc -mtriple=xtensa -mcpu=esp32s2 < %s | FileCheck --check-prefix=CHECK-ESP32S2 %s
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target datalayout = "e-m:e-p:32:32-v1:8:8-i64:64-i128:128-n32"
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target triple = "xtensa"
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@x = global i16 12902
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@y = global i16 0
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@z = common global i16 0
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define void @foo() nounwind {
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; CHECK-ESP32-LABEL: foo:
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; CHECK-ESP32: # %bb.0: # %entry
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; CHECK-ESP32-NEXT: entry a1, 32
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; CHECK-ESP32-NEXT: l32r a6, .LCPI0_0
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; CHECK-ESP32-NEXT: l16ui a10, a6, 0
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; CHECK-ESP32-NEXT: l32r a8, .LCPI0_1
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; CHECK-ESP32-NEXT: callx8 a8
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; CHECK-ESP32-NEXT: or a7, a10, a10
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; CHECK-ESP32-NEXT: l32r a8, .LCPI0_2
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; CHECK-ESP32-NEXT: l16ui a10, a8, 0
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; CHECK-ESP32-NEXT: l32r a8, .LCPI0_3
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; CHECK-ESP32-NEXT: callx8 a8
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; CHECK-ESP32-NEXT: wfr f8, a10
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; CHECK-ESP32-NEXT: wfr f9, a7
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; CHECK-ESP32-NEXT: add.s f8, f9, f8
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; CHECK-ESP32-NEXT: rfr a10, f8
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; CHECK-ESP32-NEXT: l32r a8, .LCPI0_4
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; CHECK-ESP32-NEXT: callx8 a8
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; CHECK-ESP32-NEXT: s16i a10, a6, 0
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; CHECK-ESP32-NEXT: retw.n
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;
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; CHECK-ESP32S2-LABEL: foo:
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; CHECK-ESP32S2: # %bb.0: # %entry
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; CHECK-ESP32S2-NEXT: entry a1, 32
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; CHECK-ESP32S2-NEXT: l32r a6, .LCPI0_0
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; CHECK-ESP32S2-NEXT: l16ui a10, a6, 0
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; CHECK-ESP32S2-NEXT: l32r a8, .LCPI0_1
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; CHECK-ESP32S2-NEXT: callx8 a8
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; CHECK-ESP32S2-NEXT: or a7, a10, a10
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; CHECK-ESP32S2-NEXT: l32r a8, .LCPI0_2
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; CHECK-ESP32S2-NEXT: l16ui a10, a8, 0
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; CHECK-ESP32S2-NEXT: l32r a8, .LCPI0_3
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; CHECK-ESP32S2-NEXT: callx8 a8
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; CHECK-ESP32S2-NEXT: or a11, a10, a10
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; CHECK-ESP32S2-NEXT: l32r a8, .LCPI0_4
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; CHECK-ESP32S2-NEXT: or a10, a7, a7
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; CHECK-ESP32S2-NEXT: callx8 a8
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; CHECK-ESP32S2-NEXT: l32r a8, .LCPI0_5
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; CHECK-ESP32S2-NEXT: callx8 a8
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; CHECK-ESP32S2-NEXT: s16i a10, a6, 0
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; CHECK-ESP32S2-NEXT: retw.n
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entry:
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%0 = load i16, ptr @x, align 2
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%1 = load i16, ptr @y, align 2
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%2 = tail call float @llvm.convert.from.fp16.f32(i16 %0)
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%3 = tail call float @llvm.convert.from.fp16.f32(i16 %1)
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%4 = fadd float %2, %3
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%5 = tail call i16 @llvm.convert.to.fp16.f32(float %4)
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store i16 %5, ptr @x, align 2
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ret void
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}
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define double @test_from_fp16(i16 %in) {
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; CHECK-ESP32-LABEL: test_from_fp16:
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; CHECK-ESP32: .cfi_startproc
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; CHECK-ESP32-NEXT: # %bb.0:
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; CHECK-ESP32-NEXT: entry a1, 32
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; CHECK-ESP32-NEXT: .cfi_def_cfa_offset 32
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; CHECK-ESP32-NEXT: or a10, a2, a2
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; CHECK-ESP32-NEXT: l32r a8, .LCPI1_0
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; CHECK-ESP32-NEXT: callx8 a8
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; CHECK-ESP32-NEXT: l32r a8, .LCPI1_1
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; CHECK-ESP32-NEXT: callx8 a8
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; CHECK-ESP32-NEXT: or a2, a10, a10
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; CHECK-ESP32-NEXT: or a3, a11, a11
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; CHECK-ESP32-NEXT: retw.n
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;
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; CHECK-ESP32S2-LABEL: test_from_fp16:
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; CHECK-ESP32S2: .cfi_startproc
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; CHECK-ESP32S2-NEXT: # %bb.0:
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; CHECK-ESP32S2-NEXT: entry a1, 32
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; CHECK-ESP32S2-NEXT: .cfi_def_cfa_offset 32
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; CHECK-ESP32S2-NEXT: l32r a8, .LCPI1_0
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; CHECK-ESP32S2-NEXT: and a10, a2, a8
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; CHECK-ESP32S2-NEXT: l32r a8, .LCPI1_1
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; CHECK-ESP32S2-NEXT: callx8 a8
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; CHECK-ESP32S2-NEXT: l32r a8, .LCPI1_2
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; CHECK-ESP32S2-NEXT: callx8 a8
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; CHECK-ESP32S2-NEXT: or a2, a10, a10
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; CHECK-ESP32S2-NEXT: or a3, a11, a11
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; CHECK-ESP32S2-NEXT: retw.n
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%val = call double @llvm.convert.from.fp16.f64(i16 %in)
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ret double %val
96+
}
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98+
define i16 @test_to_fp16(double %in) {
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; CHECK-ESP32-LABEL: test_to_fp16:
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; CHECK-ESP32: .cfi_startproc
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; CHECK-ESP32-NEXT: # %bb.0:
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; CHECK-ESP32-NEXT: entry a1, 32
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; CHECK-ESP32-NEXT: .cfi_def_cfa_offset 32
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; CHECK-ESP32-NEXT: or a11, a3, a3
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; CHECK-ESP32-NEXT: or a10, a2, a2
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; CHECK-ESP32-NEXT: l32r a8, .LCPI2_0
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; CHECK-ESP32-NEXT: callx8 a8
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; CHECK-ESP32-NEXT: or a2, a10, a10
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; CHECK-ESP32-NEXT: retw.n
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;
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; CHECK-ESP32S2-LABEL: test_to_fp16:
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; CHECK-ESP32S2: .cfi_startproc
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; CHECK-ESP32S2-NEXT: # %bb.0:
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; CHECK-ESP32S2-NEXT: entry a1, 32
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; CHECK-ESP32S2-NEXT: .cfi_def_cfa_offset 32
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; CHECK-ESP32S2-NEXT: or a11, a3, a3
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; CHECK-ESP32S2-NEXT: or a10, a2, a2
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; CHECK-ESP32S2-NEXT: l32r a8, .LCPI2_0
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; CHECK-ESP32S2-NEXT: callx8 a8
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; CHECK-ESP32S2-NEXT: or a2, a10, a10
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; CHECK-ESP32S2-NEXT: retw.n
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%val = call i16 @llvm.convert.to.fp16.f64(double %in)
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ret i16 %val
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}
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; Function Attrs: nounwind
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define dso_local float @cvt(half %a) unnamed_addr #0 {
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; CHECK-ESP32-LABEL: cvt:
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; CHECK-ESP32: .cfi_startproc
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; CHECK-ESP32-NEXT: # %bb.0: # %start
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; CHECK-ESP32-NEXT: entry a1, 32
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; CHECK-ESP32-NEXT: .cfi_def_cfa_offset 32
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; CHECK-ESP32-NEXT: or a10, a2, a2
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; CHECK-ESP32-NEXT: l32r a8, .LCPI3_0
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; CHECK-ESP32-NEXT: callx8 a8
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; CHECK-ESP32-NEXT: or a2, a10, a10
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; CHECK-ESP32-NEXT: retw.n
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;
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; CHECK-ESP32S2-LABEL: cvt:
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; CHECK-ESP32S2: .cfi_startproc
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; CHECK-ESP32S2-NEXT: # %bb.0: # %start
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; CHECK-ESP32S2-NEXT: entry a1, 32
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; CHECK-ESP32S2-NEXT: .cfi_def_cfa_offset 32
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; CHECK-ESP32S2-NEXT: l32r a8, .LCPI3_0
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; CHECK-ESP32S2-NEXT: and a10, a2, a8
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; CHECK-ESP32S2-NEXT: l32r a8, .LCPI3_1
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; CHECK-ESP32S2-NEXT: callx8 a8
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; CHECK-ESP32S2-NEXT: or a2, a10, a10
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; CHECK-ESP32S2-NEXT: retw.n
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start:
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%_0 = fpext half %a to float
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ret float %_0
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}
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declare float @llvm.convert.from.fp16.f32(i16) nounwind readnone
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declare double @llvm.convert.from.fp16.f64(i16) nounwind readnone
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declare i16 @llvm.convert.to.fp16.f32(float) nounwind readnone
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declare i16 @llvm.convert.to.fp16.f64(double) nounwind readnone

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