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wangpc-ppwangpc-pp
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Use INITIALIZE_PASS and make it CFG-only
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8 files changed

+2
-19
lines changed

8 files changed

+2
-19
lines changed

Diff for: ‎llvm/lib/CodeGen/MachineRegisterClassInfo.cpp

+2-6
Original file line numberDiff line numberDiff line change
@@ -16,12 +16,8 @@
1616

1717
using namespace llvm;
1818

19-
INITIALIZE_PASS_BEGIN(MachineRegisterClassInfoWrapperPass,
20-
"machine-reg-class-info",
21-
"Machine Register Class Info Analysis", false, true)
22-
INITIALIZE_PASS_END(MachineRegisterClassInfoWrapperPass,
23-
"machine-reg-class-info",
24-
"Machine Register Class Info Analysis", false, true)
19+
INITIALIZE_PASS(MachineRegisterClassInfoWrapperPass, "machine-reg-class-info",
20+
"Machine Register Class Info Analysis", true, true)
2521

2622
MachineRegisterClassInfoAnalysis::Result
2723
MachineRegisterClassInfoAnalysis::run(MachineFunction &MF,

Diff for: ‎llvm/test/CodeGen/AArch64/O3-pipeline.ll

-2
Original file line numberDiff line numberDiff line change
@@ -174,7 +174,6 @@
174174
; CHECK-NEXT: Machine Register Class Info Analysis
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; CHECK-NEXT: Register Coalescer
176176
; CHECK-NEXT: Rename Disconnected Subregister Components
177-
; CHECK-NEXT: Machine Register Class Info Analysis
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; CHECK-NEXT: Machine Instruction Scheduler
179178
; CHECK-NEXT: AArch64 Post Coalescer pass
180179
; CHECK-NEXT: Machine Block Frequency Analysis
@@ -204,7 +203,6 @@
204203
; CHECK-NEXT: MachinePostDominator Tree Construction
205204
; CHECK-NEXT: Lazy Machine Block Frequency Analysis
206205
; CHECK-NEXT: Machine Optimization Remark Emitter
207-
; CHECK-NEXT: Machine Register Class Info Analysis
208206
; CHECK-NEXT: Shrink Wrapping analysis
209207
; CHECK-NEXT: Prologue/Epilogue Insertion & Frame Finalization
210208
; CHECK-NEXT: Machine Late Instructions Cleanup Pass

Diff for: ‎llvm/test/CodeGen/AMDGPU/llc-pipeline.ll

-4
Original file line numberDiff line numberDiff line change
@@ -351,7 +351,6 @@
351351
; GCN-O1-NEXT: Register Coalescer
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; GCN-O1-NEXT: Rename Disconnected Subregister Components
353353
; GCN-O1-NEXT: Rewrite Partial Register Uses
354-
; GCN-O1-NEXT: Machine Register Class Info Analysis
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; GCN-O1-NEXT: Machine Instruction Scheduler
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; GCN-O1-NEXT: SI Whole Quad Mode
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; GCN-O1-NEXT: SI optimize exec mask operations pre-RA
@@ -663,7 +662,6 @@
663662
; GCN-O1-OPTS-NEXT: Register Coalescer
664663
; GCN-O1-OPTS-NEXT: Rename Disconnected Subregister Components
665664
; GCN-O1-OPTS-NEXT: Rewrite Partial Register Uses
666-
; GCN-O1-OPTS-NEXT: Machine Register Class Info Analysis
667665
; GCN-O1-OPTS-NEXT: Machine Instruction Scheduler
668666
; GCN-O1-OPTS-NEXT: AMDGPU Pre-RA optimizations
669667
; GCN-O1-OPTS-NEXT: SI Whole Quad Mode
@@ -981,7 +979,6 @@
981979
; GCN-O2-NEXT: Register Coalescer
982980
; GCN-O2-NEXT: Rename Disconnected Subregister Components
983981
; GCN-O2-NEXT: Rewrite Partial Register Uses
984-
; GCN-O2-NEXT: Machine Register Class Info Analysis
985982
; GCN-O2-NEXT: Machine Instruction Scheduler
986983
; GCN-O2-NEXT: AMDGPU Pre-RA optimizations
987984
; GCN-O2-NEXT: SI Whole Quad Mode
@@ -1313,7 +1310,6 @@
13131310
; GCN-O3-NEXT: Register Coalescer
13141311
; GCN-O3-NEXT: Rename Disconnected Subregister Components
13151312
; GCN-O3-NEXT: Rewrite Partial Register Uses
1316-
; GCN-O3-NEXT: Machine Register Class Info Analysis
13171313
; GCN-O3-NEXT: Machine Instruction Scheduler
13181314
; GCN-O3-NEXT: AMDGPU Pre-RA optimizations
13191315
; GCN-O3-NEXT: SI Whole Quad Mode

Diff for: ‎llvm/test/CodeGen/ARM/O3-pipeline.ll

-2
Original file line numberDiff line numberDiff line change
@@ -106,7 +106,6 @@
106106
; CHECK-NEXT: Live Interval Analysis
107107
; CHECK-NEXT: Lazy Machine Block Frequency Analysis
108108
; CHECK-NEXT: Machine Optimization Remark Emitter
109-
; CHECK-NEXT: Machine Register Class Info Analysis
110109
; CHECK-NEXT: Modulo Software Pipelining
111110
; CHECK-NEXT: MachineDominator Tree Construction
112111
; CHECK-NEXT: Machine Natural Loop Construction
@@ -129,7 +128,6 @@
129128
; CHECK-NEXT: Machine Register Class Info Analysis
130129
; CHECK-NEXT: Register Coalescer
131130
; CHECK-NEXT: Rename Disconnected Subregister Components
132-
; CHECK-NEXT: Machine Register Class Info Analysis
133131
; CHECK-NEXT: Machine Instruction Scheduler
134132
; CHECK-NEXT: Machine Block Frequency Analysis
135133
; CHECK-NEXT: Debug Variable Analysis

Diff for: ‎llvm/test/CodeGen/LoongArch/opt-pipeline.ll

-1
Original file line numberDiff line numberDiff line change
@@ -122,7 +122,6 @@
122122
; LAXX-NEXT: Machine Register Class Info Analysis
123123
; LAXX-NEXT: Register Coalescer
124124
; LAXX-NEXT: Rename Disconnected Subregister Components
125-
; LAXX-NEXT: Machine Register Class Info Analysis
126125
; LAXX-NEXT: Machine Instruction Scheduler
127126
; LAXX-NEXT: LoongArch Dead register definitions
128127
; LAXX-NEXT: Machine Block Frequency Analysis

Diff for: ‎llvm/test/CodeGen/PowerPC/O3-pipeline.ll

-1
Original file line numberDiff line numberDiff line change
@@ -164,7 +164,6 @@
164164
; CHECK-NEXT: Machine Register Class Info Analysis
165165
; CHECK-NEXT: Register Coalescer
166166
; CHECK-NEXT: Rename Disconnected Subregister Components
167-
; CHECK-NEXT: Machine Register Class Info Analysis
168167
; CHECK-NEXT: Machine Instruction Scheduler
169168
; CHECK-NEXT: PowerPC VSX FMA Mutation
170169
; CHECK-NEXT: Machine Natural Loop Construction

Diff for: ‎llvm/test/CodeGen/RISCV/O3-pipeline.ll

-2
Original file line numberDiff line numberDiff line change
@@ -114,7 +114,6 @@
114114
; CHECK-NEXT: Machine code sinking
115115
; CHECK-NEXT: Peephole Optimizations
116116
; CHECK-NEXT: Remove dead machine instructions
117-
; CHECK-NEXT: Machine Register Class Info Analysis
118117
; CHECK-NEXT: Machine Trace Metrics
119118
; CHECK-NEXT: Lazy Machine Block Frequency Analysis
120119
; CHECK-NEXT: Machine InstCombiner
@@ -138,7 +137,6 @@
138137
; CHECK-NEXT: Machine Register Class Info Analysis
139138
; CHECK-NEXT: Register Coalescer
140139
; CHECK-NEXT: Rename Disconnected Subregister Components
141-
; CHECK-NEXT: Machine Register Class Info Analysis
142140
; CHECK-NEXT: Machine Instruction Scheduler
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; CHECK-NEXT: Machine Block Frequency Analysis
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; CHECK-NEXT: Debug Variable Analysis

Diff for: ‎llvm/test/CodeGen/X86/opt-pipeline.ll

-1
Original file line numberDiff line numberDiff line change
@@ -144,7 +144,6 @@
144144
; CHECK-NEXT: Machine Register Class Info Analysis
145145
; CHECK-NEXT: Register Coalescer
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; CHECK-NEXT: Rename Disconnected Subregister Components
147-
; CHECK-NEXT: Machine Register Class Info Analysis
148147
; CHECK-NEXT: Machine Instruction Scheduler
149148
; CHECK-NEXT: Machine Block Frequency Analysis
150149
; CHECK-NEXT: Debug Variable Analysis

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