[RISCV] RISCVInstrInfo::insertIndirectBranch uses X27 without checking for RV32E/RV64E.

[topperc]

RISCVInstrInfo::insertIndirectBranch hardcodes X27, but this isn't a valid register for RV32E/RV64E.

[llvmbot]

@llvm/issue-subscribers-backend-risc-v

Author: Craig Topper (topperc)

RISCVInstrInfo::insertIndirectBranch hardcodes X27, but this isn't a valid register for RV32E/RV64E.

[lenary]

I wonder if we should have a metabug for rve issues, but I am not sure who's using rve.