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backend:AArch64good first issuehttps://github.com/llvm/llvm-project/contributehttps://github.com/llvm/llvm-project/contributellvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well
Description
define <16 x i8> @clmulr_v16i8(<16 x i8> %a, <16 x i8> %b) {
%a.ext = zext <16 x i8> %a to <16 x i16>
%b.ext = zext <16 x i8> %b to <16 x i16>
%clmul = call <16 x i16> @llvm.clmul.v16i16(<16 x i16> %a.ext, <16 x i16> %b.ext)
%res.ext = lshr <16 x i16> %clmul, splat (i16 7)
%res = trunc <16 x i16> %res.ext to <16 x i8>
ret <16 x i8> %res
}https://rust.godbolt.org/z/49qjzGfM6
It looks to be infinitely folding bitreverse(clmul(bitreverse(x),bitreverse(y))) <->clmulr(x,y)
Most likely a legal operation check is missing
Related to #182039
clmulh has a similar issue:
define <16 x i8> @clmulh_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
%a.ext = zext <16 x i8> %a to <16 x i16>
%b.ext = zext <16 x i8> %b to <16 x i16>
%clmul = call <16 x i16> @llvm.clmul.v16i16(<16 x i16> %a.ext, <16 x i16> %b.ext)
%res.ext = lshr <16 x i16> %clmul, splat (i16 8)
%res = trunc <16 x i16> %res.ext to <16 x i8>
ret <16 x i8> %res
}Reactions are currently unavailable
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backend:AArch64good first issuehttps://github.com/llvm/llvm-project/contributehttps://github.com/llvm/llvm-project/contributellvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well