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Issues list

[MIPS] llc crashes with "Using an undefined physical register" when using global register variable backend:MIPS crash Prefer [crash-on-valid] or [crash-on-invalid] llvm:regalloc
#136132 opened Apr 17, 2025 by el-ev
3
[LLDB] MIPS, incorrect byte order issues with Cast and p/x backend:MIPS lldb
#135840 opened Apr 15, 2025 by patryk4815
2
[LLDB] MIPS has missing aliases for register backend:MIPS lldb
#135839 opened Apr 15, 2025 by patryk4815
2
[Mips] Presence of inline asm instructions affects ELF ABI info backend:MIPS miscompilation
#135283 opened Apr 10, 2025 by alexrp
1
[MIPS] Compiler crash when using -O3 backend:MIPS crash Prefer [crash-on-valid] or [crash-on-invalid]
#134916 opened Apr 8, 2025 by hpoussin
4
[MIPS][COFF] Missing support for thread local variables backend:MIPS
#134915 opened Apr 8, 2025 by hpoussin
1
[MIPS] Function named Leave* or Local* are refused backend:MIPS
#134914 opened Apr 8, 2025 by hpoussin
2
[MIPS] Compiler crash when using __builtin_unreachable backend:MIPS
#134913 opened Apr 8, 2025 by hpoussin
1
1
MIPS/ASM: may optimize SW + ADDIU backend:MIPS missed-optimization
#132685 opened Mar 24, 2025 by wzssyqa
5
MIPS: trap is not needed if divisor is not zero backend:MIPS missed-optimization
#130629 opened Mar 10, 2025 by wzssyqa
1
@yingopq
2
Miscompilation when targeting mipsel with -static-pie backend:MIPS miscompilation
#124681 opened Jan 28, 2025 by Gelbpunkt
5
[llvm][Mips] After c4a60c9d343, Assertion failed: (PhysReg.isPhysical() && "Unallocated register?!"), function useOrDefCSROrFI backend:MIPS crash-on-valid llvm:codegen
#118215 opened Dec 1, 2024 by DimitryAndric
3
[Mips] out of range PC16 fixup when linking the Zig compiler for some target triples backend:MIPS
#112010 opened Oct 11, 2024 by alexrp
4
MIPS tail calls are disabled by default at all optimization levels backend:MIPS
#107730 opened Sep 7, 2024 by InBetweenNames
3
[llvm][Mips] Assembler does not assemble j $ra correctly for r6 backend:MIPS
#107460 opened Sep 5, 2024 by alexrp
5
MIPS: wrong qNaN encoding for r2 from IR backend:MIPS
#100495 opened Jul 25, 2024 by wzssyqa
1
[MIPS64] Failure to remove random NOPs in the middle of instructions backend:MIPS missed-optimization
#99783 opened Jul 20, 2024 by GabrielRavier
1
2
[MIPS] microMIPS and MIPS16 don't use jr instruction delay slot and instead always use the version with no delay slot backend:MIPS
#98560 opened Jul 11, 2024 by GabrielRavier
1
LLVM miscompiles passing/returning half on several backends by using lossy conversions backend:Hexagon backend:MIPS backend:PowerPC backend:Sparc backend:WebAssembly floating-point Floating-point math miscompilation
#97981 opened Jul 8, 2024 by beetrees
3 of 7 tasks
9
LLVM miscompiles consecutive half operations by using too much precision on several backends backend:AVR backend:Hexagon backend:loongarch backend:m68k backend:MIPS backend:MSP430 backend:PowerPC backend:Sparc backend:WebAssembly floating-point Floating-point math miscompilation
#97975 opened Jul 7, 2024 by beetrees
3 of 11 tasks
20
GlobalISel: Use G_UADDE when narrowing G_UMULH backend:AArch64 backend:AMDGPU backend:MIPS backend:RISC-V llvm:globalisel
#97194 opened Jun 30, 2024 by arsenm Loading…
22
MIPSr5+MSA: Support FMAX/FMIN instructions backend:MIPS
#90321 opened Apr 27, 2024 by wzssyqa
@wzssyqa @Cyanoxygen
2
MIPS: should use memcpy if unaligned access is long with lb/lh etc backend:MIPS
#82737 opened Feb 23, 2024 by wzssyqa
1
mips1 target generates invalid instruction backend:MIPS
#80554 opened Feb 3, 2024 by cmccord-dev
1
1
Incorrect Output with -O3 Optimization on MIPS64 Due to Complex Type Casting and Nested Loop Structure backend:MIPS llvm:optimizations miscompilation
#70495 opened Oct 27, 2023 by gyuminb
2
ProTip! Updated in the last three days: updated:>2025-04-17.