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Issues list

[RFC][TableGen] Require DAG argument for complex operands in InstAlias backend:AArch64 backend:ARM backend:PowerPC tablegen
#136411 opened Apr 19, 2025 by s-barannikov Loading…
1
[LLVM] llvm.fptosi.sat.* and llvm.fptoui.sat.* generate suboptimal code on PowerPC targets backend:PowerPC missed-optimization
#136315 opened Apr 18, 2025 by johnplatts
2
[PowerPC] Add load/store support for v2048i1 and DMF cryptography instructions backend:PowerPC llvm:ir mc Machine (object) code
#136145 opened Apr 17, 2025 by maryammo Loading…
@maryammo
2
PowerPC/VSX: Select FMINNUM and FMAXNUM backend:PowerPC
#135739 opened Apr 15, 2025 by wzssyqa Loading…
2
[LV] Move VPlan-based calculateRegisterUsage to VPlanAnalysis (NFC). backend:PowerPC backend:RISC-V llvm:transforms vectorizers
#135673 opened Apr 14, 2025 by fhahn Loading…
3
[PowerPC] Intrinsics and tests for dmr insert/extract backend:PowerPC llvm:ir
#135653 opened Apr 14, 2025 by RolandF77 Loading…
2
[CostModel] Remove optional from InstructionCost::getValue() backend:AArch64 backend:AMDGPU backend:PowerPC backend:RISC-V backend:SystemZ backend:X86 function-specialization llvm:analysis llvm:support llvm:transforms vectorizers
#135596 opened Apr 14, 2025 by davemgreen Loading…
6
[Asan][RISCV] Enhance getTgtMemIntrinsic() to allow Asan instrument t… backend:AArch64 backend:AMDGPU backend:PowerPC backend:RISC-V compiler-rt:sanitizer llvm:analysis llvm:transforms
#135198 opened Apr 10, 2025 by HankChang736 Loading…
10
[X86][DAGCombiner][SelectionDAG] - Fold Zext Build Vector to Bitcast of widen Build Vector backend:PowerPC backend:SystemZ backend:WebAssembly backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#135010 opened Apr 9, 2025 by rohitaggarwal007 Loading…
7
[driver] return immediately in addArchSpecificRPath and getArchSpecificLibPaths on AIX backend:PowerPC clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang Clang issues not falling into any other category
#134520 opened Apr 6, 2025 by DanielCChen Loading…
@DanielCChen
1
Reland "RegisterCoalescer: Add implicit-def of super register when coalescing SUBREG_TO_REG" backend:AArch64 backend:AMDGPU backend:PowerPC backend:X86 llvm:regalloc
#134408 opened Apr 4, 2025 by sdesmalen-arm Loading…
6
release/20.x: [GlobalMerge][PPC] Don't merge globals in llvm.metadata section (#131801) backend:PowerPC
#134052 opened Apr 2, 2025 by llvmbot Loading… LLVM 20.X Release
4
[PowerPC] Enable indiviual crbits tracking at -O2 backend:PowerPC clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category
#133617 opened Mar 30, 2025 by mustartt Loading…
14
[AIX] LLVM data layout is incorrect unless overridden by clang backend:PowerPC platform:aix
#133599 opened Mar 29, 2025 by workingjubilee
5
clang 19 or 20 miscompiles llvm::MergeBasicBlockIntoOnlyPred for PPC32 backend:PowerPC miscompilation
#133507 opened Mar 28, 2025 by kernigh
2
[powerpc] Assertion failure using llvm-mc -show-encoding with plxv backend:PowerPC
#133345 opened Mar 27, 2025 by efriedma-quic
1
[PowerPC][MachineLICM] Aggressively hoist CP loads with PC-Rel backend:PowerPC
#133313 opened Mar 27, 2025 by lei137 Loading…
@lei137
4
[PowerPC] Add dense math half-precision floating-point outer-product accumulate to DMR instructions backend:PowerPC llvm:ir mc Machine (object) code
#133272 opened Mar 27, 2025 by maryammo Loading…
@maryammo
1
[PowerPC] Add dense math bfloat16 floating-point outer-product accumulate to DMR instructions backend:PowerPC llvm:ir mc Machine (object) code
#133109 opened Mar 26, 2025 by maryammo Loading…
@maryammo
3
[LoopVectorizer] Prune VFs based on plan register pressure backend:PowerPC backend:RISC-V llvm:transforms vectorizers
#132190 opened Mar 20, 2025 by SamTebbs33 Loading…
74
[GlobalIsel] Avoid aligning alloca size. backend:AArch64 backend:PowerPC backend:SystemZ backend:X86 llvm:globalisel llvm:SelectionDAG SelectionDAGISel as well
#132064 opened Mar 19, 2025 by jcogan-nv Loading…
14
[PHIElimination] Reuse existing COPY in predecessor basic block backend:AArch64 backend:AMDGPU backend:ARM backend:Hexagon backend:loongarch backend:PowerPC backend:SystemZ backend:X86 debuginfo llvm:globalisel llvm:regalloc llvm:transforms
#131837 opened Mar 18, 2025 by guy-david Loading…
6
[RegisterCoalescer]: Try inflated RC for coalescing backend:AMDGPU backend:PowerPC llvm:regalloc
#130870 opened Mar 12, 2025 by jrbyrnes Loading…
13
powerpc64-ibm-aix: the .weak assembler directive is not supported backend:PowerPC crash Prefer [crash-on-valid] or [crash-on-invalid] llvm:asmparser
#130269 opened Mar 7, 2025 by folkertdev
1
[clang] Implement address sanitizer on AIX (1/n) backend:PowerPC clang:codegen IR generation bugs: mangling, exceptions, etc. clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category
#129925 opened Mar 5, 2025 by jakeegan Loading…
2
ProTip! Exclude everything labeled bug with -label:bug.