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Issues list

[RISCV] Lower SEW<=32 vector_deinterleave(2) via vunzip2{a,b} backend:RISC-V
#136463 opened Apr 19, 2025 by preames Loading…
1
Widened pointers not optimized back to scalar for vectorized interleaved accesses on RISC-V backend:RISC-V missed-optimization
#136425 opened Apr 19, 2025 by lukel97
1
[RISCV] Use ri.vzip2{a,b} for interleave2 if available backend:RISC-V
#136364 opened Apr 18, 2025 by preames Loading…
2
[RISCV] Fix Lsb > Msb case in (sra (sext_inreg X, _), C) for th.ext backend:RISC-V
#136287 opened Apr 18, 2025 by tclin914 Loading…
2
[RISCV][TTI] Use processShuffleMask for shuffle legalization estimate backend:RISC-V llvm:analysis llvm:transforms
#136191 opened Apr 17, 2025 by preames Loading…
4
[RISCV] Guard CFI emission code with MF.needsFrameMoves() backend:RISC-V
#136060 opened Apr 16, 2025 by s-barannikov Loading…
7
[llvm] annotate interfaces in llvm/Support for DLL export backend:AMDGPU backend:Hexagon backend:RISC-V llvm:support
#136014 opened Apr 16, 2025 by andrurogerz Loading…
12
Missed optimization on in-order RISC-V backend:RISC-V missed-optimization
#135860 opened Apr 15, 2025 by chadaustin
3
RISC-V: Support vectorizing FMINIMUMNUM and FMAXIMUMNUM backend:RISC-V llvm:transforms
#135727 opened Apr 15, 2025 by wzssyqa Loading…
8
[LV] Move VPlan-based calculateRegisterUsage to VPlanAnalysis (NFC). backend:PowerPC backend:RISC-V llvm:transforms vectorizers
#135673 opened Apr 14, 2025 by fhahn Loading…
3
[CostModel] Remove optional from InstructionCost::getValue() backend:AArch64 backend:AMDGPU backend:PowerPC backend:RISC-V backend:SystemZ backend:X86 function-specialization llvm:analysis llvm:support llvm:transforms vectorizers
#135596 opened Apr 14, 2025 by davemgreen Loading…
6
[IA][RISCV] Add support for vp.load/vp.store with shufflevector backend:AArch64 backend:ARM backend:RISC-V backend:X86 llvm:ir
#135445 opened Apr 11, 2025 by mshockwave Loading…
22
[RISCV] Add support for vendor relocations on Xqci extensions backend:RISC-V mc Machine (object) code
#135400 opened Apr 11, 2025 by svs-quic Loading…
11
[RISCV] Add TuneNoDefaultUnroll to generic CPUs backend:RISC-V
#135318 opened Apr 11, 2025 by wangpc-pp Loading…
1
6
[Asan][RISCV] Enhance getTgtMemIntrinsic() to allow Asan instrument t… backend:AArch64 backend:AMDGPU backend:PowerPC backend:RISC-V compiler-rt:sanitizer llvm:analysis llvm:transforms
#135198 opened Apr 10, 2025 by HankChang736 Loading…
10
[RISCV] Allocate Feature Bits for Zilsd/Zclsd/Zcmp backend:RISC-V compiler-rt:builtins compiler-rt
#135197 opened Apr 10, 2025 by lenary Loading…
12
[RISC-V] Machine Block Placement generates extra jump instructions that are not cleaned up. backend:RISC-V
#135188 opened Apr 10, 2025 by stefanp-synopsys
8
[RISCV] Add Andes XAndesperf (Andes Performance) extension. backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang Clang issues not falling into any other category mc Machine (object) code
#135110 opened Apr 10, 2025 by tclin914 Loading…
27
[RISCV] Non-base vector intrinsics not available via __attribute__((target("arch=..."))) backend:RISC-V clang:headers Headers provided by Clang, e.g. for intrinsics
#134962 opened Apr 9, 2025 by dzaima
@4vtomat
2
[RISCV] Widen i1 AnyOf reductions backend:RISC-V
#134898 opened Apr 8, 2025 by lukel97 Loading…
1
4
[RISCV] Add branch folding before branch relaxation backend:RISC-V llvm:globalisel llvm:transforms
#134760 opened Apr 8, 2025 by mikhailramalho Loading…
21
[RISC-V] clang++ 20 fails to compile highway backend:RISC-V clang Clang issues not falling into any other category regression:20 Regression in 20 release
#134730 opened Apr 7, 2025 by andreas-schwab
4
[RISC-V] RegisterCoalescer: Assertion `A.valno == B.valno && "Cannot overlap different values"' failed. backend:RISC-V crash Prefer [crash-on-valid] or [crash-on-invalid] generated by fuzzer llvm:codegen
#134424 opened Apr 4, 2025 by ewlu
3
[RISCV] llvm::is_contained is suboptimal compared to X86/AArch64 backend:RISC-V llvm:SLPVectorizer llvm:transforms missed-optimization
#134272 opened Apr 3, 2025 by wangpc-pp
1
3
[CodeGen] Use pimpl idiom for CVTables (NFC) backend:ARM backend:loongarch backend:RISC-V backend:X86 clang:codegen IR generation bugs: mangling, exceptions, etc. clang:openmp OpenMP related changes to Clang clang Clang issues not falling into any other category debuginfo
#134217 opened Apr 3, 2025 by nikic Loading…
3
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