Skip to content

Issues: llvm/llvm-project

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Clear current search query, filters, and sorts
1,366 Open 4,582 Closed
1,366 Open 4,582 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Issues list

[X86][SATCVT] Reduce MIN/MAXSS/D by conversion instruction result backend:X86
#136471 opened Apr 20, 2025 by phoebewang Loading…
1
3
[X86][APX] Combine (X86Sub 0, AND(X, Y)) to (X86And X, Y) for CLOAD/CSTORE backend:X86
#136429 opened Apr 19, 2025 by phoebewang Loading…
1
[llvm-mca][FeatureRequest] Itimeline graph, note source of delay for each instruction backend:AMDGPU backend:X86 tools:llvm-mca
#136423 opened Apr 19, 2025 by sommersun Loading…
5
Inefficient codegen for copysign(known_zero_sign_bit, x) backend:X86 missed-optimization
#136368 opened Apr 18, 2025 by dzaima
5
[LLVM] llvm.fptosi.sat.* and llvm.fptoui.sat.* generate suboptimal code in some cases on x86 backend:X86 missed-optimization
#136342 opened Apr 18, 2025 by johnplatts
1
5
[CodeGen] Inline stack guard check on Windows backend:AArch64 backend:X86 debuginfo llvm:globalisel llvm:SelectionDAG SelectionDAGISel as well
#136290 opened Apr 18, 2025 by omjavaid Loading…
4
[X86] Target feature implication mismatch with GCC backend:X86
#136209 opened Apr 17, 2025 by sayantn
7
[CUDA][HIP] Add a __device__ version of std::__glibcxx_assert_fail() backend:X86 clang:headers Headers provided by Clang, e.g. for intrinsics clang Clang issues not falling into any other category
#136133 opened Apr 17, 2025 by jmmartinez Loading…
@jmmartinez
7
[X86][AVX2] X86FixupVectorConstantsPass - performance regression backend:X86
#135998 opened Apr 16, 2025 by nurmukhametov
@RKSimon
5
[X86] combineCONCAT_VECTORS - fold concat(extract_subvector(X,0),extract_subvector(Y,0)) --> shuffle(X,Y) backend:X86
#135985 opened Apr 16, 2025 by RKSimon Loading…
3
[HLSL] Implement the faceforward intrinsic backend:SPIR-V backend:X86 clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang:headers Headers provided by Clang, e.g. for intrinsics clang Clang issues not falling into any other category HLSL HLSL Language Support llvm:ir
#135878 opened Apr 15, 2025 by kmpeng Loading…
1
19
[X86][AVX] Match v4f64 blend from shuffle of scalar values. backend:X86
#135753 opened Apr 15, 2025 by PeddleSpam Loading…
8
Mark the last use of EFLAGS before the copy's def as a kill if the copy's def operand is itself a kill. backend:X86
#135726 opened Apr 15, 2025 by AZero13 Loading…
4
[X86] Stop emitting CFI instructions on i386-windows backend:X86
#135648 opened Apr 14, 2025 by s-barannikov Loading…
4
[CostModel] Remove optional from InstructionCost::getValue() backend:AArch64 backend:AMDGPU backend:PowerPC backend:RISC-V backend:SystemZ backend:X86 function-specialization llvm:analysis llvm:support llvm:transforms vectorizers
#135596 opened Apr 14, 2025 by davemgreen Loading…
6
[X86] Fix RegAlloc issue by implementing TRI::getCustomEHPadPreservedMask backend:X86
#135518 opened Apr 13, 2025 by s-barannikov Loading…
10
[LLVM] APInt::tcAdd has quiet poor codegen. backend:X86 llvm:optimizations llvm:SelectionDAG SelectionDAGISel as well missed-optimization
#135486 opened Apr 12, 2025 by Ralender
3
[IA][RISCV] Add support for vp.load/vp.store with shufflevector backend:AArch64 backend:ARM backend:RISC-V backend:X86 llvm:ir
#135445 opened Apr 11, 2025 by mshockwave Loading…
22
[X86][Tablegen] ISA tablegen naming convention for record needs update backend:X86
#135379 opened Apr 11, 2025 by mahesh-attarde
1
[CodeGen] Miscompile with llvm.maximumnum.f64 and llvm.maximum.f64 backend:X86 floating-point Floating-point math miscompilation
#135313 opened Apr 11, 2025 by patrick-rivos
@RKSimon
5
[Clang][CodeGen][X86] don't coerce int128 into {i64,i64} for SysV-like ABIs backend:X86 clang:codegen IR generation bugs: mangling, exceptions, etc. clang Clang issues not falling into any other category
#135230 opened Apr 10, 2025 by T0b1-iOS Loading…
11
[CodeGen][NPM] Support generic regalloc-npm option backend:AMDGPU backend:X86
#135149 opened Apr 10, 2025 by optimisan Loading…
8
[X86][DAGCombiner][SelectionDAG] - Fold Zext Build Vector to Bitcast of widen Build Vector backend:PowerPC backend:SystemZ backend:WebAssembly backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#135010 opened Apr 9, 2025 by rohitaggarwal007 Loading…
7
[X86][SelectionDAG] Fix the Gather's base and index by modifying the Scale value backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#134979 opened Apr 9, 2025 by rohitaggarwal007 Loading…
14
[AVX-512] vpternlogq fails to be emitted for longer chains of bitmanipulations backend:X86
#134768 opened Apr 8, 2025 by Validark
1
ProTip! Find all open issues with in progress development work with linked:pr.