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Issues list

Stop abusing Twine in DiagnosticInfo backend:DirectX llvm:ir llvm:SelectionDAG SelectionDAGISel as well llvm:transforms PGO Profile Guided Optimizations
#136371 opened Apr 18, 2025 by bogner Loading…
6
[CodeGen] Inline stack guard check on Windows backend:AArch64 backend:X86 debuginfo llvm:globalisel llvm:SelectionDAG SelectionDAGISel as well
#136290 opened Apr 18, 2025 by omjavaid Loading…
4
[AArch64] Add tablegen patterns for i8 and i16 vector insert/extract pairs backend:AArch64 llvm:SelectionDAG SelectionDAGISel as well
#136091 opened Apr 17, 2025 by davemgreen Loading…
1
[DEBUGINFO] Propagate debug metadata for sext SDNode. backend:NVPTX debuginfo llvm:SelectionDAG SelectionDAGISel as well
#135971 opened Apr 16, 2025 by apeskov Loading…
8
CodeGen: Add ISD::AssertNoFPClass llvm:SelectionDAG SelectionDAGISel as well
#135946 opened Apr 16, 2025 by wzssyqa Loading…
6
SelectionDAG: Fix isKnownNeverNaN for Min and Max backend:AMDGPU llvm:SelectionDAG SelectionDAGISel as well
#135742 opened Apr 15, 2025 by wzssyqa Loading…
3
[LLVM] APInt::tcAdd has quiet poor codegen. backend:X86 llvm:optimizations llvm:SelectionDAG SelectionDAGISel as well missed-optimization
#135486 opened Apr 12, 2025 by Ralender
3
[SelectionDAG] Improve value type selection for inline asm within selected register class backend:NVPTX llvm:SelectionDAG SelectionDAGISel as well
#135097 opened Apr 9, 2025 by dlee992 Loading…
6
[X86][DAGCombiner][SelectionDAG] - Fold Zext Build Vector to Bitcast of widen Build Vector backend:PowerPC backend:SystemZ backend:WebAssembly backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#135010 opened Apr 9, 2025 by rohitaggarwal007 Loading…
7
[X86][SelectionDAG] Fix the Gather's base and index by modifying the Scale value backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#134979 opened Apr 9, 2025 by rohitaggarwal007 Loading…
14
[DAGCombiner] Option --combiner-select-seq backend:AArch64 llvm:SelectionDAG SelectionDAGISel as well
#134813 opened Apr 8, 2025 by ppetrovic98 Loading…
17
[GISel] Add KnownFPClass Analysis to GISelValueTrackingPass llvm:analysis llvm:globalisel llvm:SelectionDAG SelectionDAGISel as well
#134611 opened Apr 7, 2025 by tgymnich Loading…
9
[NFC] Use std::move to avoid copy backend:X86 llvm:SelectionDAG SelectionDAGISel as well tablegen
#134531 opened Apr 6, 2025 by abhishek-kaushik22 Loading…
3
[DAGCombiner] Don't fold cheap extracts of multiple use splats backend:AArch64 llvm:SelectionDAG SelectionDAGISel as well
#134120 opened Apr 2, 2025 by lukel97 Loading…
8
[DAG][AArch64] Handle truncated buildvectors to allow and(subvector(anyext)) fold. backend:AArch64 llvm:SelectionDAG SelectionDAGISel as well
#133915 opened Apr 1, 2025 by davemgreen Loading…
8
Add IR and codegen support for deactivation symbols. backend:AArch64 llvm:globalisel llvm:ir llvm:SelectionDAG SelectionDAGISel as well tablegen
#133536 opened Mar 28, 2025 by pcc Loading…
4
[AArch64] Custom lower v4i8 subreg extract. backend:AArch64 llvm:SelectionDAG SelectionDAGISel as well
#133438 opened Mar 28, 2025 by davemgreen Loading…
6
[RISCV] Ideas around store merging in DAGCombine backend:RISC-V llvm:SelectionDAG SelectionDAGISel as well
#132787 opened Mar 24, 2025 by preames
2
[AMDGPU][SDAG] Only fold flat offsets if they are inbounds backend:AMDGPU llvm:SelectionDAG SelectionDAGISel as well llvm:transforms
#132353 opened Mar 21, 2025 by ritter-x2a Loading…
5
[GlobalIsel] Avoid aligning alloca size. backend:AArch64 backend:PowerPC backend:SystemZ backend:X86 llvm:globalisel llvm:SelectionDAG SelectionDAGISel as well
#132064 opened Mar 19, 2025 by jcogan-nv Loading…
14
[SDAG] Handle insert_subvector in isKnownNeverNaN backend:AMDGPU llvm:SelectionDAG SelectionDAGISel as well
#131989 opened Mar 19, 2025 by tclin914 Loading…
7
[SDAG] Introduce inbounds flag for pointer arithmetic backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#131862 opened Mar 18, 2025 by ritter-x2a Loading…
14
[NVPTX] Add TLI hook for load slice cost and implement it backend:NVPTX llvm:SelectionDAG SelectionDAGISel as well
#131847 opened Mar 18, 2025 by AlexMaclean Loading…
@AlexMaclean
6
[LoongArch] ICE on SIMD code with SIMD disabled backend:loongarch crash Prefer [crash-on-valid] or [crash-on-invalid] llvm:SelectionDAG SelectionDAGISel as well
#131771 opened Mar 18, 2025 by xen0n
1
[WIP][AMDGPU] Fix emitting illegal COPY backend:AMDGPU llvm:SelectionDAG SelectionDAGISel as well
#131752 opened Mar 18, 2025 by PankajDwivedi-25 • Draft
6
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