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Issues list

[MIPS] llc crashes with "Using an undefined physical register" when using global register variable backend:MIPS crash Prefer [crash-on-valid] or [crash-on-invalid] llvm:regalloc
#136132 opened Apr 17, 2025 by el-ev
3
need help on the code in RegAllocGreedy.cpp->tryAssign() llvm:regalloc question A question, not bug report. Check out https://llvm.org/docs/GettingInvolved.html instead!
#135997 opened Apr 16, 2025 by BaoshanPang
[GreedyRegAlloc] Multiple spill reloads into same register without intermediate def/overwrite llvm:regalloc
#135639 opened Apr 14, 2025 by JanekvO
2
Address Codegen bug related to marking subregister MachineOperand defines as undef backend:AMDGPU llvm:regalloc
#134929 opened Apr 8, 2025 by bababuck Loading…
1
11
[RegisterCoalescer]: Try inflated RC for coalescing reg->subreg backend:AMDGPU llvm:regalloc
#134438 opened Apr 4, 2025 by jrbyrnes Loading…
5
Reland "RegisterCoalescer: Add implicit-def of super register when coalescing SUBREG_TO_REG" backend:AArch64 backend:AMDGPU backend:PowerPC backend:X86 llvm:regalloc
#134408 opened Apr 4, 2025 by sdesmalen-arm Loading…
6
[InlineSpiller] Check rematerialization before folding operand backend:X86 llvm:regalloc
#134015 opened Apr 2, 2025 by weiguozhi Loading…
18
[PHIElimination] Reuse existing COPY in predecessor basic block backend:AArch64 backend:AMDGPU backend:ARM backend:Hexagon backend:loongarch backend:PowerPC backend:SystemZ backend:X86 debuginfo llvm:globalisel llvm:regalloc llvm:transforms
#131837 opened Mar 18, 2025 by guy-david Loading…
6
[CodeGen] commuteInstruction should update implicit-def backend:X86 llvm:codegen llvm:regalloc
#131361 opened Mar 14, 2025 by sdesmalen-arm Loading…
9
[RegisterCoalescer]: Try inflated RC for coalescing backend:AMDGPU backend:PowerPC llvm:regalloc
#130870 opened Mar 12, 2025 by jrbyrnes Loading…
13
[CodeGen][NPM] Port VirtRegRewriter to NPM backend:AMDGPU backend:X86 llvm:codegen llvm:regalloc
#130564 opened Mar 10, 2025 by optimisan Loading…
9
MachineVerifier does not diagnose REG_SEQUENCE with overlapping input operands accepts-invalid llvm:codegen llvm:regalloc
#130075 opened Mar 6, 2025 by arsenm
[AMDGPU][NPM] Support -regalloc-npm options backend:AMDGPU llvm:regalloc
#129035 opened Feb 27, 2025 by optimisan Loading…
13
Suboptimal register use on x86-64 backend:X86 llvm:regalloc
#128722 opened Feb 25, 2025 by tavianator
6
AMDGPU should try to shrink 64-bit defs to 32-bit when rematerializing backend:AMDGPU llvm:regalloc missed-optimization
#128716 opened Feb 25, 2025 by arsenm
1
LiveIntervals: Use BumpPtrAllocator llvm:regalloc
#127057 opened Feb 13, 2025 by arsenm Loading…
9
AMDGPU: No live subrange at use for an undef subreg right after LIS creation with partially defined register backend:AMDGPU llvm:regalloc
#125948 opened Feb 5, 2025 by rampitec
1
Lousy spilling in the RegAlloc's llvm:regalloc
#124350 opened Jan 24, 2025 by Bob64375
Use not jointly dominated by defs during scheduling with overlapping register tuple defs llvm:codegen llvm:regalloc
#123301 opened Jan 17, 2025 by arsenm
[TableGen][GISel] Create untyped registers during instruction selection backend:AMDGPU llvm:globalisel llvm:regalloc tablegen
#121270 opened Dec 28, 2024 by s-barannikov Loading…
24
[SystemZ] Bad machine code: Illegal virtual register for instruction backend:SystemZ llvm:regalloc
#121232 opened Dec 27, 2024 by JonPsson1
1
[CodeGen] Add MachineRegisterClassInfo analysis pass backend:AArch64 backend:AMDGPU backend:ARM backend:loongarch backend:PowerPC backend:X86 llvm:regalloc
#120690 opened Dec 20, 2024 by wangpc-pp Loading…
30
RegAllocGreedy: Fix subrange based instruction split logic backend:AMDGPU llvm:regalloc
#120199 opened Dec 17, 2024 by arsenm Loading…
9
CodeGen: Treat subreg-to-subreg copies as isFullCopyInstr backend:AMDGPU llvm:regalloc
#120056 opened Dec 16, 2024 by arsenm Loading…
6
Crash with -enable-ipra for trivial internal linkage functions for RISC-V/AArch64/Arm backend:AArch64 backend:ARM backend:RISC-V crash Prefer [crash-on-valid] or [crash-on-invalid] ipo Interprocedural optimizations llvm:regalloc
#119556 opened Dec 11, 2024 by asb
5
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