Change logic behind JTAG tap selection to make instrustions work for the demo platform #137
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@marnovandermaas is there any chance you can review this please? |
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Thanks for putting this together. I was trying to make the Sonata target work but didn't have much luck. The main reason why I'm marking this PR as "request changes" is that it also breaks the Verilator simulator, which now also looks for the BSCANE tap. We need to find a solution for this before we can merge this in.
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@heliosfa can you check the latest commit that I put on this PR? This works correctly on Sonata and simulator but it would be good to check the other targets. |
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Should be fixed with latest commit.
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Ok, I've now tested this on the Arty A7 as well, so I think this is safe to merge. Please feel free to open up another issue if you have issues with any of the other boards. |
This commit fixes a deficiency of our version of FuseSoC. Previously it would always use the JTAG TAP, which only works with Sonata and simulation. This is because flags were not implemented yet. Instead, this commit uses the synth flag to set whether to use the BSCANE TAP or the JTAG TAP. Co-authored-by: Marno van der Maas <[email protected]>
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The current instructions fail to work for the demo platform when used with the native Python environment as noted in #116 as the upstream version of FuseSoC does not support tags.
This PR flips the logic surrounding the tags so that the Bscane tap is used by default as this is what is needed for most FPGA-based platforms. Sonata is the obvious exception, so a note has been added to the README.
I've based this off of #136 as that is already approved for merge.