[top-i2c,dv] Added chip level I2C Device TX_RX test#633
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KinzaQamar
requested review from
elliotb-lowrisc,
engdoreis,
marnovandermaas,
martin-velay and
ziuziakowska
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engdoreis
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I left a suggestion, otherwise it LGTM.
| VOLATILE_WRITE(i2c->txdata, txdata); | ||
| } | ||
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| void i2c_clear_cmd_complete(i2c_t i2c) |
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I suggest making a function to clear interrupts that take the interrupt as argument like uart:
mocha/sw/device/lib/hal/uart.c
Line 36 in 3b3b9e2
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…vice Signed-off-by: Kinza Qamar <kqzaman@lowrisc.org>
Signed-off-by: Kinza Qamar <kqzaman@lowrisc.org>
Signed-off-by: Kinza Qamar <kqzaman@lowrisc.org>
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| sw_sys_clk_period_ns[0]); | ||
| fall_cycles = round_up_divide({sw_fall_time_ns[1], sw_fall_time_ns[0]}, | ||
| sw_sys_clk_period_ns[0]); | ||
| endtask |
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Nit: most of your new methods are long enough to justify the fact to add the label, I feel it hard to read without it.
| @@ -37,23 +69,42 @@ function int unsigned top_chip_dv_i2c_tx_rx_vseq::round_up_divide(int unsigned a | |||
| endfunction | |||
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| function void top_chip_dv_i2c_tx_rx_vseq::configure_agent_timing(); | |||
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I think these changes also have an impact on top_chip_dv_i2c_host_tx_rx_vseq. Isn't it an issue?
| // De-allocate the xfer item in order to send a new transfer | ||
| xfer = null; |
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This is dead code and can be dropped
| const uint16_t setup_start_time_ns = 4700; | ||
| const uint16_t hold_start_time_ns = 4000; | ||
| const uint16_t setup_stop_time_ns = 4000; | ||
| const uint16_t hold_stop_time_ns = 4700; |
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Nit: hold_stop_time_ns is actually bus-free time (tBUF) per the I2C spec, not a hold time on the stop condition — same concept as bus_free_time_cycles in i2c_timing_params_t (i2c.h). Same naming carries through to sw_hold_stop_time_ns/stop_hold_cycles in top_chip_dv_i2c_tx_rx_vseq.sv and the backdoor-read in top_chip_dv_i2c_device_tx_rx_vseq.sv. Could you either rename to bus_free_time_ns/bus_free_cycles for consistency, or add a short comment noting it maps to tBUF?
martin-velay
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martin-velay
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Added a host Vseq and device SW. The host will initiate read / write transfer. The device SW waits for the transfers to finish and compare the data bytes in each transfer at the end