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[otbn] Add OTBN simulator implementation of SIMD instructions #18738

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[otbn] Add OTBN simulator implementation of SIMD instructions

[otbn] Add OTBN simulator implementation of SIMD instructions #18738

Triggered via pull request February 10, 2026 07:51
@etterlietterli
synchronize #29232
etterli:otbn-pqc-simd-sim
Status Cancelled
Total duration 1h 51m 10s
Artifacts 22

ci.yml

on: pull_request
Lint (quick)
2m 54s
Lint (quick)
Earl Grey for CW340  /  Build bitstream
1h 0m
Earl Grey for CW340 / Build bitstream
Earl Grey for CW310 Hyperdebug  /  Build bitstream
39m 10s
Earl Grey for CW310 Hyperdebug / Build bitstream
Lint (slow)
12m 40s
Lint (slow)
Build documentation
5m 11s
Build documentation
Airgapped build
18m 22s
Airgapped build
Verible lint
1m 3s
Verible lint
Run OTBN smoke Test
2m 48s
Run OTBN smoke Test
Run OTBN crypto tests
30m 59s
Run OTBN crypto tests
Verilated English Breakfast
5m 31s
Verilated English Breakfast
Verilated Earl Grey
15m 45s
Verilated Earl Grey
CW305's Bitstream
26m 32s
CW305's Bitstream
Build Docker Containers
2m 20s
Build Docker Containers
Build and test software
24m 37s
Build and test software
Build and test Darjeeling software
14m 41s
Build and test Darjeeling software
QEMU smoketest
2m 9s
QEMU smoketest
Test QEMU local development override
4m 47s
Test QEMU local development override
CW340 Test ROM Tests  /  FPGA test
4m 40s
CW340 Test ROM Tests / FPGA test
CW340 ROM Tests  /  FPGA test
11m 52s
CW340 ROM Tests / FPGA test
CW340 ROM_EXT Tests  /  FPGA test
18m 58s
CW340 ROM_EXT Tests / FPGA test
CW340 SiVal Tests  /  FPGA test
18m 59s
CW340 SiVal Tests / FPGA test
CW340 SiVal ROM_EXT Tests  /  FPGA test
18m 59s
CW340 SiVal ROM_EXT Tests / FPGA test
CW340 Manufacturing Tests  /  FPGA test
18m 59s
CW340 Manufacturing Tests / FPGA test
CW310 Test ROM Tests  /  FPGA test
3m 24s
CW310 Test ROM Tests / FPGA test
CW310 ROM Tests  /  FPGA test
36m 5s
CW310 ROM Tests / FPGA test
CW310 ROM_EXT Tests  /  FPGA test
21m 50s
CW310 ROM_EXT Tests / FPGA test
CW310 SiVal Tests  /  FPGA test
18m 4s
CW310 SiVal Tests / FPGA test
CW310 SiVal ROM_EXT Tests  /  FPGA test
5m 17s
CW310 SiVal ROM_EXT Tests / FPGA test
CW310 Manufacturing Tests  /  FPGA test
10m 51s
CW310 Manufacturing Tests / FPGA test
Cache bitstreams to GCP
2s
Cache bitstreams to GCP
Verify FPGA jobs
0s
Verify FPGA jobs
Merge blocker
3s
Merge blocker
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Annotations

19 errors and 1 warning
Verilated English Breakfast
Process completed with exit code 1.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Process completed with exit code 1.
Build and test software
Process completed with exit code 1.
bash.sw/device/silicon_creator/rom_ext/e2e/rescue/std_utils/usbdfu_protocol_fpga_cw310_rom_ext.bash: bash#L1
exited with error code 1
CW310 ROM_EXT Tests / FPGA test
Process completed with exit code 3.
CW340 ROM_EXT Tests / FPGA test
Canceling since a higher priority waiting request for CI-refs/pull/29232/merge exists
CW340 ROM_EXT Tests / FPGA test
The operation was canceled.
CW340 SiVal Tests / FPGA test
Canceling since a higher priority waiting request for CI-refs/pull/29232/merge exists
CW340 SiVal Tests / FPGA test
The operation was canceled.
CW340 Manufacturing Tests / FPGA test
Canceling since a higher priority waiting request for CI-refs/pull/29232/merge exists
CW340 Manufacturing Tests / FPGA test
The operation was canceled.
CW340 SiVal ROM_EXT Tests / FPGA test
Canceling since a higher priority waiting request for CI-refs/pull/29232/merge exists
CW340 SiVal ROM_EXT Tests / FPGA test
The operation was canceled.
CI
Canceling since a higher priority waiting request for CI-refs/pull/29232/merge exists
CI
Canceling since a higher priority waiting request for CI-refs/pull/29232/merge exists
CI
Canceling since a higher priority waiting request for CI-refs/pull/29232/merge exists
CI
Canceling since a higher priority waiting request for CI-refs/pull/29232/merge exists
CI
Canceling since a higher priority waiting request for CI-refs/pull/29232/merge exists
Verilated English Breakfast
No files were found with the provided path: build-bin/hw/top_englishbreakfast/Vchip_englishbreakfast_verilator. No artifacts will be uploaded.

Artifacts

Produced during runtime
Name Size Digest
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execute_rom_ext_fpga_tests_cw310-targets
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execute_test_rom_fpga_tests_cw310-test-results
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partial-build-bin-chip_earlgrey_cw310_hyperdebug
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sw_build_test-test-results
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verilator_earlgrey-test-results
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