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@etterli etterli commented Feb 2, 2026

This PR is based upon #29231 (first 3 commits) and adds the simulator implementation for the new vectorized instructions.

Note, merging this PR will not yet resolve the issue that DV tests fail due to illegal instructions. For this the actual RTL implementation is also required.

@etterli etterli requested a review from a team as a code owner February 2, 2026 16:29
@etterli etterli requested review from andrea-caforio, h-filali, johannheyszl, nasahlpa, rswarbrick and vogelpi and removed request for a team February 2, 2026 16:29
@etterli etterli force-pushed the otbn-pqc-simd-sim branch 4 times, most recently from 2366588 to 4aa8f12 Compare February 3, 2026 07:20
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I've been using this code for months at this point without problems.

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Some initial notes (I got as far as BNMULV).

It looks really nice though!

@etterli etterli force-pushed the otbn-pqc-simd-sim branch 2 times, most recently from 98e6442 to d2fd698 Compare February 4, 2026 12:28
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Some notes here about the rest of the "Add vectorized bignum instructions" commit.

Lots of nitty notes (sorry), but I really like this! My inner functional programmer wishes that we could write things as maps over lists of lane elements that get glued together at the end, but that's a dream for a follow-up, I think :-D

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I've left a couple of notes about the penultimate commit.

For the last one, are you sure we actually need to check the files in? Rather than checking in a load of auto-generated text, I think it would be much better to check the testbench so that it can generate them on the fly.

@etterli etterli force-pushed the otbn-pqc-simd-sim branch 2 times, most recently from ee3d5e0 to bdc2c64 Compare February 6, 2026 13:59
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etterli commented Feb 6, 2026

@rswarbrick Thanks for the review! I adapted the points and also extended the simulator test framework that it now autogenerates most of the SIMD tests. The remaining non-generated tests are not worth the effort to write a script to auto-generate them.

@etterli etterli force-pushed the otbn-pqc-simd-sim branch 2 times, most recently from d3e52b7 to d17596c Compare February 6, 2026 14:19
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This is really great! Thanks!

@rswarbrick rswarbrick added this pull request to the merge queue Feb 9, 2026
@github-merge-queue github-merge-queue bot removed this pull request from the merge queue due to failed status checks Feb 9, 2026
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Thanks for the implementation & addressing all feedback!

Before merging this, we should first merge #29231 and rebase this PR afterwards.

@etterli etterli force-pushed the otbn-pqc-simd-sim branch 2 times, most recently from de7f0f7 to 545e76e Compare February 10, 2026 09:41
This adds the vectorized instructions to the OTBN simulator.

Signed-off-by: Pascal Etterli <[email protected]>
…r test cases

The vectorized instruction simulator implementation is tested against simple test programs. This
adds a script which generates such programs instead of writing them by hand.

Signed-off-by: Pascal Etterli <[email protected]>
This commit adds simple tests to test the simulator implementation of the vectorized instructions.
Most of these tests are autogenerated when running a test using the generate_bn_simd_tests.py scripts.

Signed-off-by: Pascal Etterli <[email protected]>
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etterli commented Feb 11, 2026

This PR is now rebased upon #29231 and also #29296. It is now ready to merge.

@andrea-caforio andrea-caforio added the CI:Rerun Rerun failed CI jobs label Feb 11, 2026
@github-actions github-actions bot removed the CI:Rerun Rerun failed CI jobs label Feb 11, 2026
@nasahlpa nasahlpa added this pull request to the merge queue Feb 11, 2026
Merged via the queue into lowRISC:master with commit 3495f85 Feb 11, 2026
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4 participants