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[otbn] Add OTBN simulator implementation of SIMD instructions #18746

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[otbn] Add OTBN simulator implementation of SIMD instructions

[otbn] Add OTBN simulator implementation of SIMD instructions #18746

Triggered via pull request February 10, 2026 09:41
@etterlietterli
synchronize #29232
etterli:otbn-pqc-simd-sim
Status Success
Total duration 3h 31m 3s
Artifacts 30

ci.yml

on: pull_request
Lint (quick)
3m 5s
Lint (quick)
Earl Grey for CW310 Hyperdebug  /  Build bitstream
38m 45s
Earl Grey for CW310 Hyperdebug / Build bitstream
Earl Grey for CW340  /  Build bitstream
1h 5m
Earl Grey for CW340 / Build bitstream
Lint (slow)
12m 42s
Lint (slow)
Build documentation
4m 52s
Build documentation
Airgapped build
17m 28s
Airgapped build
Verible lint
1m 11s
Verible lint
Run OTBN smoke Test
2m 36s
Run OTBN smoke Test
Run OTBN crypto tests
34m 13s
Run OTBN crypto tests
Verilated English Breakfast
5m 47s
Verilated English Breakfast
Verilated Earl Grey
14m 59s
Verilated Earl Grey
CW305's Bitstream
26m 54s
CW305's Bitstream
Build Docker Containers
2m 16s
Build Docker Containers
Build and test software
21m 53s
Build and test software
Build and test Darjeeling software
14m 58s
Build and test Darjeeling software
QEMU smoketest
2m 8s
QEMU smoketest
Test QEMU local development override
4m 41s
Test QEMU local development override
CW310 Test ROM Tests  /  FPGA test
3m 58s
CW310 Test ROM Tests / FPGA test
CW310 ROM Tests  /  FPGA test
36m 16s
CW310 ROM Tests / FPGA test
CW310 ROM_EXT Tests  /  FPGA test
20m 46s
CW310 ROM_EXT Tests / FPGA test
CW310 SiVal Tests  /  FPGA test
18m 42s
CW310 SiVal Tests / FPGA test
CW310 SiVal ROM_EXT Tests  /  FPGA test
5m 12s
CW310 SiVal ROM_EXT Tests / FPGA test
CW310 Manufacturing Tests  /  FPGA test
10m 14s
CW310 Manufacturing Tests / FPGA test
Cache bitstreams to GCP
4s
Cache bitstreams to GCP
CW340 Test ROM Tests  /  FPGA test
4m 1s
CW340 Test ROM Tests / FPGA test
CW340 ROM Tests  /  FPGA test
10m 3s
CW340 ROM Tests / FPGA test
CW340 ROM_EXT Tests  /  FPGA test
30m 17s
CW340 ROM_EXT Tests / FPGA test
CW340 SiVal Tests  /  FPGA test
26m 50s
CW340 SiVal Tests / FPGA test
CW340 SiVal ROM_EXT Tests  /  FPGA test
35m 32s
CW340 SiVal ROM_EXT Tests / FPGA test
CW340 Manufacturing Tests  /  FPGA test
43m 0s
CW340 Manufacturing Tests / FPGA test
Merge blocker
3s
Merge blocker
Verify FPGA jobs
40s
Verify FPGA jobs
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4 errors and 1 warning
Verilated English Breakfast
Process completed with exit code 1.
Lint (slow)
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Lint (slow)
Process completed with exit code 1.
Build and test software
Process completed with exit code 1.
Verilated English Breakfast
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Artifacts

Produced during runtime
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