[rv_core_ibex,rtl] Use a LockstepDelay of 1 cycle
#18827
github-merge-queue[bot]ci.yml
on: push
Lint (quick)
3m 28s
Earl Grey for CW310 Hyperdebug
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Build bitstream
1m 16s
Lint (slow)
13m 55s
Build documentation
7m 11s
Airgapped build
18m 42s
Verible lint
0s
Run OTBN smoke Test
3m 31s
Run OTBN crypto tests
4m 27s
Verilated English Breakfast
5m 59s
Verilated Earl Grey
1h 34m
CW305's Bitstream
29m 25s
Build Docker Containers
1m 26s
Build and test software
22m 16s
Build and test Darjeeling software
16m 28s
QEMU smoketest
2m 49s
Test QEMU local development override
5m 0s
CW340 Test ROM Tests
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FPGA test
29m 7s
CW340 ROM Tests
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FPGA test
44m 31s
CW340 ROM_EXT Tests
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FPGA test
1h 0m
CW340 SiVal Tests
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FPGA test
59m 9s
CW340 SiVal ROM_EXT Tests
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FPGA test
1h 0m
CW340 Manufacturing Tests
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FPGA test
1h 0m
CW310 Test ROM Tests
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FPGA test
29m 27s
CW310 ROM Tests
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FPGA test
CW310 ROM_EXT Tests
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FPGA test
53m 30s
CW310 SiVal Tests
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FPGA test
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CW310 SiVal ROM_EXT Tests
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FPGA test
31m 26s
CW310 Manufacturing Tests
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FPGA test
48m 25s
Merge blocker
3s
Verify FPGA jobs
Annotations
13 errors and 1 warning
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Build Docker Containers
buildx failed with: ERROR: failed to build: failed to solve: process "/bin/sh -c curl -f -Ls -o verible.tar.gz https://github.com/chipsalliance/verible/releases/download/${VERIBLE_VERSION}/verible-${VERIBLE_VERSION}-linux-static-x86_64.tar.gz && mkdir -p /tools/verible && tar -C /tools/verible -xf verible.tar.gz --strip-components=1" did not complete successfully: exit code: 22
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Verilated English Breakfast
Process completed with exit code 1.
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Lint (slow)
Process completed with exit code 1.
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Lint (slow)
Process completed with exit code 1.
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Build and test software
Process completed with exit code 1.
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CW340 ROM_EXT Tests / FPGA test
The job has exceeded the maximum execution time of 1h0m0s
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CW340 ROM_EXT Tests / FPGA test
The operation was canceled.
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CW340 SiVal ROM_EXT Tests / FPGA test
The job has exceeded the maximum execution time of 1h0m0s
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CW340 SiVal ROM_EXT Tests / FPGA test
The operation was canceled.
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CW340 Manufacturing Tests / FPGA test
The job has exceeded the maximum execution time of 1h0m0s
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CW340 Manufacturing Tests / FPGA test
The operation was canceled.
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CW310 SiVal Tests / FPGA test
Process completed with exit code 1.
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CW310 SiVal Tests / FPGA test
Process completed with exit code 37.
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Verilated English Breakfast
No files were found with the provided path: build-bin/hw/top_englishbreakfast/Vchip_englishbreakfast_verilator. No artifacts will be uploaded.
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Artifacts
Produced during runtime
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execute_rom_ext_fpga_tests_cw310-targets
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execute_sival_rom_ext_fpga_tests_cw310-targets
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238 Bytes |
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execute_sival_rom_ext_fpga_tests_cw310-test-results
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16.1 KB |
sha256:bb68dca1725d2969b6f2396a64bdb8fba099ce50fb02be9ba13ee37ab158bfdf
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execute_test_rom_fpga_tests_cw310-targets
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314 Bytes |
sha256:0f952c03e32c1b35a6ab2357613150cef2dad09f24d67a67c3099fc02fa39e8f
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execute_test_rom_fpga_tests_cw310-test-results
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execute_test_rom_fpga_tests_cw340-targets
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execute_test_rom_fpga_tests_cw340-test-results
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partial-build-bin-chip_earlgrey_cw310_hyperdebug
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verilator_earlgrey-test-results
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