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[otbn,sim] Add simulator test cases for bignum vectorized instructions
This commit adds simple tests to test the simulator implementation of the vectorized instructions. Signed-off-by: Pascal Etterli <[email protected]>
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# Copyright lowRISC contributors (OpenTitan project).
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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# AUTOGENERATED with generate_bn_simd_tests.py --seed 5627
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w0 = 0xffffffff38e982e4e08a278ff53b68c7adf3591712562ba8423010eafe4b043c
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w1 = 0x9a8ee1130000000042fb3f9785ae6563d4cff0ddabe7e2cd2ba9e523604c5f59
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w20 = 0x9a8ee11238e982e4238567267ae9ce2a82c349f4be3e0e756dd9f60d5e976395
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/* Copyright lowRISC contributors (OpenTitan project). */
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/* Licensed under the Apache License, Version 2.0, see LICENSE for details. */
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/* SPDX-License-Identifier: Apache-2.0 */
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/* AUTOGENERATED with generate_bn_simd_tests.py --seed 5627 */
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.section .text.start
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/* Load vectors */
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addi x2, x0, 0
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la x3, vec32a0
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bn.lid x2++, 0(x3)
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la x3, vec32b0
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bn.lid x2++, 0(x3)
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/* Run test */
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bn.addv.8s w20, w0, w1
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/* Clean up */
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addi x2, x0, 0 /* reset x2 */
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addi x3, x0, 0 /* reset x3 */
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ecall
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.section .data
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/*
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32-bit vector vec32a0 for instruction bn.addv.8s
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vec32a0 = [4294967295, 954827492, 3767150479, 4114311367, 2918406423, 307637160, 1110446314, 4266329148]
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vec32a0 = 0xffffffff38e982e4e08a278ff53b68c7adf3591712562ba8423010eafe4b043c
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*/
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vec32a0:
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.word 0xfe4b043c
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.word 0x423010ea
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.word 0x12562ba8
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.word 0xadf35917
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.word 0xf53b68c7
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.word 0xe08a278f
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.word 0x38e982e4
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.word 0xffffffff
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/*
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32-bit vector vec32b0 for instruction bn.addv.8s
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vec32b0 = [2593054995, 0, 1123762071, 2242798947, 3570397405, 2884100813, 732554531, 1615617881]
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vec32b0 = 0x9a8ee1130000000042fb3f9785ae6563d4cff0ddabe7e2cd2ba9e523604c5f59
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*/
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vec32b0:
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.word 0x604c5f59
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.word 0x2ba9e523
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.word 0xabe7e2cd
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.word 0xd4cff0dd
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.word 0x85ae6563
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.word 0x42fb3f97
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.word 0x00000000
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.word 0x9a8ee113
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/*
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Result of bn.addv.8s (w20)
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res = [2593054994, 954827492, 595945254, 2062143018, 2193836532, 3191737973, 1843000845, 1586979733]
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res = 0x9a8ee11238e982e4238567267ae9ce2a82c349f4be3e0e756dd9f60d5e976395
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*/
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# Copyright lowRISC contributors (OpenTitan project).
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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# AUTOGENERATED with generate_bn_simd_tests.py --seed 5627
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w0 = 0x007fe000002222a6c2ec40684a3f49a8aa74b852007a4dd10032103d0065fcde
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w1 = 0x1dc7a73d00000000705669520a86e86f10ddf065000c33d700798597005f0fdd
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w20 = 0x1dc7a73c002222a632c2c9b954465216bad2c8b60006a1a7002bb5d300452cba
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w30 = 0x00000000000000000000000000000000000000000000000000000000007fe001
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/* Copyright lowRISC contributors (OpenTitan project). */
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/* Licensed under the Apache License, Version 2.0, see LICENSE for details. */
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/* SPDX-License-Identifier: Apache-2.0 */
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/* AUTOGENERATED with generate_bn_simd_tests.py --seed 5627 */
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.section .text.start
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/* Load vectors */
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addi x2, x0, 0
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la x3, vec32a0
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bn.lid x2++, 0(x3)
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la x3, vec32b0
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bn.lid x2++, 0(x3)
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/* Load modulus into MOD WSR */
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li x2, 30
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la x3, mod32
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bn.lid x2, 0(x3)
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bn.wsrw MOD, w30
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/* Run test */
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bn.addvm.8s w20, w0, w1
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/* Clean up */
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addi x2, x0, 0 /* reset x2 */
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addi x3, x0, 0 /* reset x3 */
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ecall
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.section .data
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/*
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32-bit vector mod32 for instruction bn.addvm.8s
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mod32 = [8380417]
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mod32 = 0x007fe001
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*/
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mod32:
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.word 0x007fe001
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.word 0x
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.word 0x
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.word 0x
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.word 0x
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.word 0x
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.word 0x
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.word 0x
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/*
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32-bit vector vec32a0 for instruction bn.addvm.8s
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vec32a0 = [8380416, 2237094, 3270262888, 1245661608, 2859776082, 8015313, 3280957, 6683870]
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vec32a0 = 0x007fe000002222a6c2ec40684a3f49a8aa74b852007a4dd10032103d0065fcde
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*/
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vec32a0:
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.word 0x0065fcde
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.word 0x0032103d
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.word 0x007a4dd1
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.word 0xaa74b852
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.word 0x4a3f49a8
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.word 0xc2ec4068
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.word 0x002222a6
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.word 0x007fe000
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/*
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32-bit vector vec32b0 for instruction bn.addvm.8s
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vec32b0 = [499623741, 0, 1884711250, 176613487, 282980453, 799703, 7964055, 6229981]
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vec32b0 = 0x1dc7a73d00000000705669520a86e86f10ddf065000c33d700798597005f0fdd
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*/
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vec32b0:
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.word 0x005f0fdd
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.word 0x00798597
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.word 0x000c33d7
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.word 0x10ddf065
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.word 0x0a86e86f
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.word 0x70566952
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.word 0x00000000
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.word 0x1dc7a73d
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/*
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Result of bn.addvm.8s (w20)
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res = [499623740, 2237094, 851626425, 1413894678, 3134376118, 434599, 2864595, 4533434]
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res = 0x1dc7a73c002222a632c2c9b954465216bad2c8b60006a1a7002bb5d300452cba
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*/
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# Copyright lowRISC contributors (OpenTitan project).
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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# AUTOGENERATED with generate_bn_simd_tests.py --seed 5627
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w0 = 0x00000000000000010000af710000260613873f1227790323af89087e3c08bac4
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w1 = 0x71abf6a49dda4bfd0009b75800032be141973aa1530768a28955f665c3a57045
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w20 = 0x000000009dda4bfda89f15d878966d46b1f6be5292cf34262f0f6db6ac6416d4
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/* Copyright lowRISC contributors (OpenTitan project). */
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/* Licensed under the Apache License, Version 2.0, see LICENSE for details. */
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/* SPDX-License-Identifier: Apache-2.0 */
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/* AUTOGENERATED with generate_bn_simd_tests.py --seed 5627 */
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.section .text.start
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/* Load vectors */
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addi x2, x0, 0
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la x3, vec32a0
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bn.lid x2++, 0(x3)
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la x3, vec32b0
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bn.lid x2++, 0(x3)
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/* Run test */
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bn.mulv.8s w20, w0, w1
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/* Clean up */
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addi x2, x0, 0 /* reset x2 */
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addi x3, x0, 0 /* reset x3 */
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ecall
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.section .data
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/*
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32-bit vector vec32a0 for instruction bn.mulv.8s
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vec32a0 = [0, 1, 44913, 9734, 327630610, 662242083, 2944993406, 1007205060]
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vec32a0 = 0x00000000000000010000af710000260613873f1227790323af89087e3c08bac4
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*/
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vec32a0:
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.word 0x3c08bac4
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.word 0xaf89087e
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.word 0x27790323
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.word 0x13873f12
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.word 0x00002606
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.word 0x0000af71
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.word 0x00000001
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.word 0x00000000
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/*
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32-bit vector vec32b0 for instruction bn.mulv.8s
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vec32b0 = [1907095204, 2648329213, 636760, 207841, 1100429985, 1392994466, 2304112229, 3282399301]
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vec32b0 = 0x71abf6a49dda4bfd0009b75800032be141973aa1530768a28955f665c3a57045
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*/
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vec32b0:
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.word 0xc3a57045
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.word 0x8955f665
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.word 0x530768a2
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.word 0x41973aa1
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.word 0x00032be1
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.word 0x0009b758
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.word 0x9dda4bfd
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.word 0x71abf6a4
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/*
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Result of bn.mulv.8s (w20)
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res = [0, 2648329213, 2828998104, 2023124294, 2985737810, 2463052838, 789540278, 2892240596]
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res = 0x000000009dda4bfda89f15d878966d46b1f6be5292cf34262f0f6db6ac6416d4
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*/
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# Copyright lowRISC contributors (OpenTitan project).
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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# AUTOGENERATED with generate_bn_simd_tests.py --seed 5627
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w0 = 0x063c6a814dc57909e25d69ecfc120be39ebf076cdb34965527bfd054d5bd8018
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w1 = 0xae9fcad4fad7d975b7e9804994386245707ea018496c569e773a2db71daae149
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w2 = 0x063c6a814dc57909e25d69ecfc120be39ebf076cdb34965527bfd054d5bd8018
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w3 = 0xae9fcad4fad7d975b7e9804994386245707ea018496c569e773a2db71daae149
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w20 = 0x377fbfc921aa6c91b973a04c5955e6bb53b709cc2f91933dc7943bf4488e9ed8
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w21 = 0x7c3b05f55f67f21d10ae74dc29f7d9bf2e4cf05c05d9c1d9c0cd6a645557e2f8
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/* Copyright lowRISC contributors (OpenTitan project). */
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/* Licensed under the Apache License, Version 2.0, see LICENSE for details. */
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/* SPDX-License-Identifier: Apache-2.0 */
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/* AUTOGENERATED with generate_bn_simd_tests.py --seed 5627 */
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.section .text.start
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/* Load vectors */
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addi x2, x0, 0
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la x3, vec32a0
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bn.lid x2++, 0(x3)
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la x3, vec32b0
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bn.lid x2++, 0(x3)
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la x3, vec32a1
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bn.lid x2++, 0(x3)
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la x3, vec32b1
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bn.lid x2++, 0(x3)
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/* Run test */
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bn.mulvl.8s w20, w0, w1, 0
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bn.mulvl.8s w21, w2, w3, 6
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/* Clean up */
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addi x2, x0, 0 /* reset x2 */
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addi x3, x0, 0 /* reset x3 */
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ecall
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.section .data
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/*
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32-bit vector vec32a0 for instruction bn.mulvl.8s
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vec32a0 = [104622721, 1304787209, 3797772780, 4229041123, 2663319404, 3677656661, 666882132, 3585966104]
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vec32a0 = 0x063c6a814dc57909e25d69ecfc120be39ebf076cdb34965527bfd054d5bd8018
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*/
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vec32a0:
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.word 0xd5bd8018
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.word 0x27bfd054
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.word 0xdb349655
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.word 0x9ebf076c
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.word 0xfc120be3
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.word 0xe25d69ec
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.word 0x4dc57909
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.word 0x063c6a81
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/*
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32-bit vector vec32a1 for instruction bn.mulvl.8s
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vec32a1 = [104622721, 1304787209, 3797772780, 4229041123, 2663319404, 3677656661, 666882132, 3585966104]
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vec32a1 = 0x063c6a814dc57909e25d69ecfc120be39ebf076cdb34965527bfd054d5bd8018
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*/
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vec32a1:
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.word 0xd5bd8018
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.word 0x27bfd054
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.word 0xdb349655
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.word 0x9ebf076c
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.word 0xfc120be3
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.word 0xe25d69ec
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.word 0x4dc57909
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.word 0x063c6a81
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/*
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32-bit vector vec32b0 for instruction bn.mulvl.8s
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vec32b0 = [2929707732, 4208449909, 3085533257, 2486723141, 1887346712, 1231836830, 2000301495, 497738057]
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vec32b0 = 0xae9fcad4fad7d975b7e9804994386245707ea018496c569e773a2db71daae149
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*/
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vec32b0:
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.word 0x1daae149
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.word 0x773a2db7
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.word 0x496c569e
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.word 0x707ea018
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.word 0x94386245
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.word 0xb7e98049
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.word 0xfad7d975
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.word 0xae9fcad4
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/*
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32-bit vector vec32b1 for instruction bn.mulvl.8s
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vec32b1 = [2929707732, 4208449909, 3085533257, 2486723141, 1887346712, 1231836830, 2000301495, 497738057]
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vec32b1 = 0xae9fcad4fad7d975b7e9804994386245707ea018496c569e773a2db71daae149
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*/
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vec32b1:
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.word 0x1daae149
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.word 0x773a2db7
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.word 0x496c569e
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.word 0x707ea018
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.word 0x94386245
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.word 0xb7e98049
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.word 0xfad7d975
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.word 0xae9fcad4
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/*
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Result of bn.mulvl.8s (w20)
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res = [931119049, 564817041, 3111362636, 1498801851, 1404504524, 798069565, 3348380660, 1217306328]
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res = 0x377fbfc921aa6c91b973a04c5955e6bb53b709cc2f91933dc7943bf4488e9ed8
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*/
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/*
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Result of bn.mulvl.8s (w21)
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res = [2084242933, 1600647709, 279868636, 704108991, 776794204, 98157017, 3234687588, 1431823096]
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res = 0x7c3b05f55f67f21d10ae74dc29f7d9bf2e4cf05c05d9c1d9c0cd6a645557e2f8
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*/
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# Copyright lowRISC contributors (OpenTitan project).
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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# AUTOGENERATED with generate_bn_simd_tests.py --seed 5627
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w0 = 0x00130ba60026b8b1007d0790003471de003b0d4400447ffa00203c06004518b8
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w1 = 0x0039f9600003d82d002cf414003383050051a57900539816002d0334007be6c9
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w20 = 0x001004e50031e6e10071a89e00190c820030776d007809e3007f8b21003d1bd3
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w30 = 0x000000000000000000000000000000000000000000000000fc7fdfff007fe001

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