[aes/dv] Add missing predict() calls to update mirrored RAL values #26425
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When using .set() method of the uvm_reg_field base class (this only updates the desired value in the abstraction class) followed by a csr_update() call (this updates the DUT in case the desired value doesn't match the mirrored value), we also need to explicitly update the mirrored value. This can happen either by using the .predict() method, or by calling csr_rd() or csr_wr(). This commit adds missing calls to the .predict() method were required. Without these calls, the mirrored values can get out of sync and since in some cases we use the mirrored value to decide whether we need to update register values, the DUT and the DV environment can get out of sync. Signed-off-by: Pirmin Vogel <[email protected]>
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rswarbrick
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Feb 26, 2025
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This seems rather strange to me. Doesn't aes_scoreboard::process_tl_access do the prediction anyway? (I think it should be aes_scoreboard.sv:259)
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Thanks for the feedback @rswarbrick , this explains why we haven't seen issues with this in many tests. @nasahlpa ran into this issue in a test that disables the scoreboard. |
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Ahah! :-D Is there anything in this PR that needs to land then? |
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I am closing this PR as it's getting superseded by #29276. |
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When using .set() method of the uvm_reg_field base class (this only updates the desired value in the abstraction class) followed by a csr_update() call (this updates the DUT in case the desired value doesn't match the mirrored value), we also need to explicitly update the mirrored value. This can happen either by using the .predict() method, or by calling csr_rd() or csr_wr(). This commit adds missing calls to the .predict() method were required.
Without these calls, the mirrored values can get out of sync and since in some cases we use the mirrored value to decide whether we need to update register values, the DUT and the DV environment can get out of sync.