WIP: Systemrdl

mypy.ini

@@ -4,5 +4,5 @@ ignore_missing_imports = True
 ignore_missing_imports = True
 [mypy-semantic_version]
 ignore_missing_imports = True
-[mypy-peakrdl_systemrdl]
+[mypy-rdlexporter]
 ignore_missing_imports = True

pyproject.toml

@@ -67,7 +67,9 @@ dependencies = [
   # Build and run tool for Design Verification flows
   "dvsim==1.34.1",
 
-  "peakrdl-systemrdl >= 1.0",
+  # Used in reggen to export register description in SystemRDL format from hjson.
+  "rdlexporter>=0.4",
+  "systemrdl-compiler>=1.32.1",
 ]
 
 [tool.setuptools]

python-requirements.txt

@@ -386,9 +386,6 @@ packaging==25.0 \
 pathspec==1.0.3 \
     --hash=sha256:bac5cf97ae2c2876e2d25ebb15078eb04d76e4b98921ee31c6f85ade8b59444d \
     --hash=sha256:e80767021c1cc524aa3fb14bedda9c34406591343cc42797b386ce7b9354fb6c
-peakrdl-systemrdl==1.0.1 \
-    --hash=sha256:17d72641ade637e5650a20589977a3452316ecb630f500907f4c579c0a8f7ebd \
-    --hash=sha256:77fe097d01d252b365f9d603e2712a85b3cf65f32c7ad52aadd1a8dea9635a5e
 pluggy==1.6.0 \
     --hash=sha256:7dcc130b76258d33b90f61b658791dede3486c3e6bfb003ee5c9bfb396dd22f3 \
     --hash=sha256:e920276dd6813095e9377c0bc5566d94c932c33b27a3e3945d8389c374dd4746
@@ -698,6 +695,9 @@ pyyaml==6.0.3 \
 questionary==2.1.1 \
     --hash=sha256:3d7e980292bb0107abaa79c68dd3eee3c561b83a0f89ae482860b181c8bd412d \
     --hash=sha256:a51af13f345f1cdea62347589fbb6df3b290306ab8930713bfae4d475a7d4a59
+rdlexporter==0.4.0 \
+    --hash=sha256:52f7208c2949addb981196fce24001f22cb4f8403c564e686510a962dae75592 \
+    --hash=sha256:c111eb51989aa1f0818422d88eb0ac54eda75661856e74cafa0721693931e775
 referencing==0.37.0 \
     --hash=sha256:381329a9f99628c9069361716891d34ad94af76e461dcb0335825aecc7692231 \
     --hash=sha256:44aefc3142c5b842538163acb373e24cce6632bd54bdb01b21ad5863489f50d8

util/reggen/BUILD

@@ -354,7 +354,9 @@ py_library(
         ":reg_block",
         ":register",
         ":window",
-        requirement("peakrdl_systemrdl"),
+        "//util/reggen/systemrdl:udp",
+        requirement("systemrdl-compiler"),
+        requirement("rdlexporter"),
     ],
 )
 

util/reggen/ip_block.py

@@ -181,6 +181,7 @@ class IpBlock:
     inter_signals: list[InterSignal]
     bus_interfaces: BusInterfaces
     clocking: Clocking
+    # Tuple with (InOut, In, Out) signals.
     xputs: tuple[Sequence[Signal], Sequence[Signal], Sequence[Signal]]
     wakeups: Sequence[Signal]
     reset_requests: Sequence[Signal]

util/reggen/systemrdl/udp.py

@@ -7,7 +7,7 @@
 from systemrdl.udp import UDPDefinition
 from systemrdl import RDLCompiler  # type: ignore[attr-defined]
 from systemrdl.node import Node
-from systemrdl.component import Reg
+from systemrdl.component import Reg, Mem, Signal
 
 
 class UDPBoolean(UDPDefinition):
@@ -29,13 +29,71 @@ class Shadowed(UDPBoolean):
     valid_components = {Reg}
 
 
+class IntegrityBypass(UDPBoolean):
+    name = "integrity_bypass"
+    valid_components = {Mem}
+
+
+class SigType(UDPDefinition):
+    default_assignment = None
+    name = "sigtype"
+    valid_components = {Signal}
+    valid_type = "SigType"
+
+    enum_map = {
+        "None": 0,
+        "Interrupt": 1,  # Signal is an interrupt
+        "Alert": 2,  # Signal is an alert
+        "InterModReqRsp": 3,  # Signal is an inter module, with type=req_rsp
+        "InterModReq": 4,  # Signal is an inter module, with type=uni and act=req
+        "InterModRecv": 5,  # Signal is an inter module, with type=uni and act=recv
+        "Output": 6,  # Signal is an output
+        "Input": 7,  # Signal is an input
+        "Inout": 8,  # Signal is input and/or output
+    }
+
+    def validate(self, node: Node, value: Any) -> None:
+        if value not in self.enum_map:
+            self.msg.error(
+                f"Invalid sigtype '{value}'. Expected one of {list(self.enum_map.keys())}"
+            )
+
+
+class InterModStruct(UDPDefinition):
+    valid_type = str
+    default_assignment = "logic"
+    name = "inter_mod_struct"
+    valid_components = {Signal}
+
+    def validate(self, node: Node, value: Any) -> None:
+        if not isinstance(value, str):
+            self.msg.error("The type of {self.name} must be string.", self.get_src_ref(node))
+
+
+class InterModPackage(UDPDefinition):
+    valid_type = str
+    name = "inter_mod_package"
+    valid_components = {Signal}
+
+    def validate(self, node: Node, value: Any) -> None:
+        if not isinstance(value, str):
+            self.msg.error("The type of {self.name} must be string.", self.get_src_ref(node))
+
+
 OPENTITAN_UDPS = Path(__file__).parent / "udp.rdl"
 
 
-def register_udps(compiler: RDLCompiler) -> None:
+def register_udps(compiler: RDLCompiler) -> Path:
     """
     Register opentitan specific UDPs (User Defined Properties)
     """
     compiler.register_udp(Hwre)
     compiler.register_udp(Shadowed)
+    # compiler.register_udp(AsyncClk)
+    compiler.register_udp(IntegrityBypass)
+    # TODO: figure out how to declare the 'valid_types' attribute when it is a user-defined enum.
+    # compiler.register_udp(SigType)
+    compiler.register_udp(InterModStruct)
+    compiler.register_udp(InterModPackage)
     compiler.compile_file(OPENTITAN_UDPS)
+    return OPENTITAN_UDPS

util/reggen/systemrdl/udp.rdl

@@ -3,6 +3,9 @@
 * SPDX-License-Identifier: Apache-2.0
 */
 
+`ifndef UDP_RDL
+`define UDP_RDL
+
 /**
  * 4-bits boolean values
  */
@@ -67,6 +70,14 @@ enum MultiBitBool32 {
   False = 0x69696969;
 };
 
+/*
+ * The same as swwe, but supports multibit references.
+ */
+property mubi_swwe {
+  type = ref;
+  component = reg|field;
+};
+
 /**
  * true if hardware uses `re` signal, which is latched signal of software read pulse.
  * The standard SystemRDL property `swacc` cannot be used here because `swacc = hwre | swmod`.
@@ -77,7 +88,8 @@ property hwre {
   default = false;
 };
 
-/* If it is true, the register will be implemented using the prim_subreg_shadow module.
+/**
+ * If it is true, the register will be implemented using the prim_subreg_shadow module.
  * Shadow registers are a mechanism to guard sensitive registers against this specific
  * type of attack. They come at a cost of increased area, and a modified SW interaction.
  */
@@ -86,3 +98,95 @@ property shadowed {
   component = reg;
   default = false;
 };
+
+/*
+ * Indicates the register must cross to a different clock domain before use.
+ * The value shown here should correspond to one of the module's clocks.
+ */
+property async_clk {
+  type = ref;
+  component = reg;
+};
+property async_rst {
+  type = ref;
+  component = reg;
+};
+
+/*
+ * If true, integrity bits are passed through directly from the memory.
+ */
+property integrity_bypass {
+  type = boolean;
+  component = mem;
+  default = false;
+};
+
+/*
+ * If true, this array was originally a compacted multi-register.
+ */
+property compacted {
+  type = boolean;
+  component = reg;
+  default = false;
+};
+
+/*
+ * Defines properties to be used inside signals.
+ * These will help to model the hjson fields: 'inter_signal_list', 'available_output_list',
+ * 'interrupt_list' and 'alert_list' as rdl signals.
+ */
+enum SigType {
+  None;
+  Interrupt;     // Signal is an interrupt
+  Alert;         // Signal is an alert
+  InterModReqRsp;// Signal is an inter module, with type=req_rsp
+  InterModReq;   // Signal is an inter module, with type=uni and act=req
+  InterModRecv;  // Signal is an inter module, with type=uni and act=recv
+  Output;        // Signal is an output
+  Input;         // Signal is an input
+  InOut;         // Signal is input and/or output
+  Sync;          // Signal is used for synchonization. i.e clock, reset.
+};
+
+property sigtype {
+  type = SigType;
+  component = signal;
+  default = SigType::None;
+};
+
+/*
+ * Defines the Inter-module signal's data structure. It is generally bundled into `struct packed`
+ * type. This `struct` is used with `package` for topgen tool to define the signal.
+ */
+property inter_mod_struct {
+  type = string;
+  component = signal;
+  default = "logic";
+};
+property inter_mod_package {
+  type = string;
+  component = signal;
+};
+
+enum BusProtocol {
+  TlUl;
+};
+
+enum BusDirection {
+  Host;
+  Device;
+};
+
+struct BusInterfaceCfg {
+  BusProtocol protocol;
+  BusDirection direction;
+  boolean racl_support;
+  string hier_path;
+};
+
+property bus_interface_cfg{
+  type = BusInterfaceCfg;
+  component = addrmap;
+};
+
+`endif