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Earlgrey-M2.5.1-RC1

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@msfschaffner msfschaffner released this 01 Jun 21:41
· 11509 commits to master since this release
Earlgrey-M2.5.1-RC1
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msfschaffner Michael Schaffner
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Overview

This is the EarlGrey Engineering Sample release candidate. All blocks are at least at D2 design stage, and V2S verification stage (except for RV_DM, I2C, RV_DM).

This is a follow up to Earlgrey-M2.5.1-RC0. All M2.5.1 releases are associated with GitHub milestone: M2.5.1.

Changes since M2.5.1-RC0

  • Several DV updates (targeting M2.5.2 release)
  • Several ROM release readiness changes (targeting M2.5.2 release)
  • Update SDC constraints for synthesis
    • [spi_device] SDC updates & Enhance pass-through rates for wider reads by pipelining the return path #11718
    • [syn] Async FIFO gray pointer timing constraints #13011
    • [top] Update interface timing constraints #18274
  • ECOs:
    • [M2.5, ECO, I2C] Restart condition violates I2C Specification #18721

Full Changelog: Earlgrey-M2.5.1-RC0...Earlgrey-M2.5.1-RC1

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