IITB-RISC Pipelined processor

This is my submission for the final project for the spring 2023 run of EE309. The objective is to program a 16-bit microprocessor in HDL.

Implementation details and how to test this is detailed in the project report, present in this repository.

Name		Name	Last commit message	Last commit date
Latest commit History 6 Commits
Testing		Testing
.gitignore		.gitignore
ALU.vhdl		ALU.vhdl
Branch_Calc.vhdl		Branch_Calc.vhdl
CPU.qsf		CPU.qsf
CPU.qws		CPU.qws
CPU.vhdl		CPU.vhdl
CPU_Testing.qpf		CPU_Testing.qpf
Data_mem.vhdl		Data_mem.vhdl
Decode_mult.vhdl		Decode_mult.vhdl
Execute.vhdl		Execute.vhdl
Incrementer.vhdl		Incrementer.vhdl
Inst_mem.vhdl		Inst_mem.vhdl
Instruction_Decoder.vhdl		Instruction_Decoder.vhdl
README.md		README.md
RegisterFile.vhdl		RegisterFile.vhdl
Report_EE302_Project_210070052.pdf		Report_EE302_Project_210070052.pdf
TestBench.vhdl		TestBench.vhdl
script.ps1		script.ps1

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