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15 changes: 9 additions & 6 deletions bsp/renesas/libraries/HAL_Drivers/nano/drv_console.c
Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,7 @@

#if defined(RT_USING_CONSOLE) && defined(RT_USING_SEMAPHORE)

static rt_sem_t console_sem = RT_NULL;
struct rt_semaphore console_sem;

#if defined(RT_NANO_CONSOLE_UART0)
#define renesas_uart_ctrl g_uart0_ctrl
Expand Down Expand Up @@ -60,8 +60,11 @@ static rt_sem_t console_sem = RT_NULL;

void rt_hw_console_init(void)
{
fsp_err_t err;
console_sem = rt_sem_create("console", 0, RT_IPC_FLAG_FIFO);
fsp_err_t err = FSP_SUCCESS;
rt_err_t res = RT_EOK;

res = rt_sem_init(&console_sem, "console", 0, RT_IPC_FLAG_FIFO);
RT_ASSERT(res == RT_EOK);

/* Initialize UART using FSP */
#ifdef SOC_SERIES_R7FA8M85
Expand All @@ -78,12 +81,12 @@ void rt_hw_console_init(void)

void console_send_byte(uint8_t ch)
{
renesas_uart_ctrl.p_reg->TDR = ch;
#if defined(SOC_SERIES_R7FA8M85) || defined(SOC_SERIES_R9A07G0)
while ((renesas_uart_ctrl.p_reg->CSR_b.TEND) == 0);
#else
while ((renesas_uart_ctrl.p_reg->SSR_b.TEND) == 0);
#endif
renesas_uart_ctrl.p_reg->TDR = ch;
}

void rt_hw_console_output(const char *str)
Expand Down Expand Up @@ -111,7 +114,7 @@ void renesas_uart_callback(uart_callback_args_t *p_args)
/* Received a character or receive completed */
case UART_EVENT_RX_CHAR:
case UART_EVENT_RX_COMPLETE:
rt_sem_release(console_sem);
rt_sem_release(&console_sem);
break;

default:
Expand All @@ -122,7 +125,7 @@ void renesas_uart_callback(uart_callback_args_t *p_args)
char rt_hw_console_getchar(void)
{
int ch = -1;
rt_sem_take(console_sem, RT_WAITING_FOREVER);
rt_sem_take(&console_sem, RT_WAITING_FOREVER);
#ifdef SOC_SERIES_R7FA8M85
fsp_err_t ret = R_SCI_B_UART_Read(&renesas_uart_ctrl, (uint8_t *)&ch, 1);
#else
Expand Down
20 changes: 4 additions & 16 deletions src/scheduler_up.c
Original file line number Diff line number Diff line change
Expand Up @@ -31,6 +31,7 @@
* 2023-03-27 rose_man Split into scheduler upc and scheduler_mp.c
* 2023-10-17 ChuShicheng Modify the timing of clearing RT_THREAD_STAT_YIELD flag bits
* 2025-08-04 Pillar Add rt_scheduler_critical_switch_flag
* 2025-08-20 RyanCW rt_scheduler_lock_nest use atomic operations
*/

#define __RT_IPC_SOURCE__
Expand All @@ -49,7 +50,7 @@ rt_uint8_t rt_thread_ready_table[32];
#endif /* RT_THREAD_PRIORITY_MAX > 32 */

extern volatile rt_atomic_t rt_interrupt_nest;
static rt_int16_t rt_scheduler_lock_nest;
static rt_atomic_t rt_scheduler_lock_nest;
rt_uint8_t rt_current_priority;

static rt_int8_t rt_scheduler_critical_switch_flag;
Expand Down Expand Up @@ -649,22 +650,9 @@ RTM_EXPORT(rt_exit_critical_safe);
*/
rt_base_t rt_enter_critical(void)
{
rt_base_t level;
rt_base_t critical_level;

/* disable interrupt */
level = rt_hw_interrupt_disable();

/*
* the maximal number of nest is RT_UINT16_MAX, which is big
* enough and does not check here
*/
rt_scheduler_lock_nest ++;
critical_level = rt_scheduler_lock_nest;

/* enable interrupt */
rt_hw_interrupt_enable(level);

critical_level = rt_atomic_add(&rt_scheduler_lock_nest, 1) + 1;
return critical_level;
}
RTM_EXPORT(rt_enter_critical);
Expand Down Expand Up @@ -722,7 +710,7 @@ RTM_EXPORT(rt_exit_critical);
*/
rt_uint16_t rt_critical_level(void)
{
return rt_scheduler_lock_nest;
return (rt_uint16_t)rt_atomic_load(&rt_scheduler_lock_nest);
}
RTM_EXPORT(rt_critical_level);

Expand Down