GitHub - mgleria/MIPS: MIPS processor implemented in Verilog

Branches Tags

Name		Name	Last commit message	Last commit date
Latest commit History 7 Commits
.Xil/PlanAhead-3092-Marta-PC/ngc2edif		.Xil/PlanAhead-3092-Marta-PC/ngc2edif
Useful documents		Useful documents
_ngo		_ngo
_xmsgs		_xmsgs
ipcore_dir		ipcore_dir
iseconfig		iseconfig
isim		isim
xlnx_auto_0_xdb		xlnx_auto_0_xdb
xst/work		xst/work
BancoRegTest.v		BancoRegTest.v
BancoRegTest_beh.prj		BancoRegTest_beh.prj
Baud_Rate.cmd_log		Baud_Rate.cmd_log
Baud_Rate.lso		Baud_Rate.lso
Baud_Rate.ngc		Baud_Rate.ngc
Baud_Rate.prj		Baud_Rate.prj
Baud_Rate.stx		Baud_Rate.stx
Baud_Rate.syr		Baud_Rate.syr
Baud_Rate.v		Baud_Rate.v
Baud_Rate.xst		Baud_Rate.xst
Baud_Rate_envsettings.html		Baud_Rate_envsettings.html
Baud_Rate_summary.html		Baud_Rate_summary.html
Baud_Rate_xst.xrpt		Baud_Rate_xst.xrpt
DebuggerRx.cmd_log		DebuggerRx.cmd_log
DebuggerRx.tfi		DebuggerRx.tfi
DebuggerRx.v		DebuggerRx.v
DebuggerRxPipeTest.v		DebuggerRxPipeTest.v
DebuggerRxPipeTest.wcfg		DebuggerRxPipeTest.wcfg
DebuggerRxPipeTest_beh.prj		DebuggerRxPipeTest_beh.prj
DebuggerRxPipeTest_isim_beh.wdb		DebuggerRxPipeTest_isim_beh.wdb
DebuggerRxTest.v		DebuggerRxTest.v
DebuggerRx_2.cmd_log		DebuggerRx_2.cmd_log
DebuggerRx_2.tfi		DebuggerRx_2.tfi
DebuggerRx_2.v		DebuggerRx_2.v
DebuggerTx.cmd_log		DebuggerTx.cmd_log
DebuggerTx.lso		DebuggerTx.lso
DebuggerTx.prj		DebuggerTx.prj
DebuggerTx.stx		DebuggerTx.stx
DebuggerTx.tfi		DebuggerTx.tfi
DebuggerTx.v		DebuggerTx.v
DebuggerTx.xst		DebuggerTx.xst
DebuggerTx_stx_beh.prj		DebuggerTx_stx_beh.prj
EX.v		EX.v
EndProgramDetector.cmd_log		EndProgramDetector.cmd_log
EndProgramDetector.tfi		EndProgramDetector.tfi
EndProgramDetector.v		EndProgramDetector.v
ExecuteTest.v		ExecuteTest.v
FF_Buf_Interface.bmm		FF_Buf_Interface.bmm
FF_Buf_Interface.prj		FF_Buf_Interface.prj
FF_Buf_Interface.stx		FF_Buf_Interface.stx
FF_Buf_Interface.v		FF_Buf_Interface.v
FF_Buf_Interface.xst		FF_Buf_Interface.xst
IFTest.v		IFTest.v
InstructionDecode.v		InstructionDecode.v
InstructionFetch.v		InstructionFetch.v
MEMTest.v		MEMTest.v
MUX2to1.v		MUX2to1.v
Memoria.v		Memoria.v
MipsProcessor.v		MipsProcessor.v
Mux.v		Mux.v
Mux5Bit.v		Mux5Bit.v
PC.v		PC.v
Pipeline.cmd_log		Pipeline.cmd_log
Pipeline.tfi		Pipeline.tfi
Pipeline.v		Pipeline.v
PipelineTest.v		PipelineTest.v
PipelineTest1.v		PipelineTest1.v
Prueba.v		Prueba.v
Prueba_beh.prj		Prueba_beh.prj
Prueba_isim_beh.wdb		Prueba_isim_beh.wdb
ROM.mif		ROM.mif
Rx.prj		Rx.prj
Rx.stx		Rx.stx
Rx.v		Rx.v
Rx.xst		Rx.xst
Test.cmd_log		Test.cmd_log
Test.lso		Test.lso
Test.prj		Test.prj
Test.stx		Test.stx
Test.tfi		Test.tfi
Test.v		Test.v
Test.xst		Test.xst
Test1.v		Test1.v
Test_stx_beh.prj		Test_stx_beh.prj
Testbench_1.v		Testbench_1.v
Testbench_1.wcfg		Testbench_1.wcfg
Testbench_1_beh.prj		Testbench_1_beh.prj
Testbench_1_isim_beh.wdb		Testbench_1_isim_beh.wdb
Testbench_1_stx_beh.prj		Testbench_1_stx_beh.prj
Top.bld		Top.bld
Top.cmd_log		Top.cmd_log
Top.lso		Top.lso
Top.ncd		Top.ncd
Top.ngc		Top.ngc
Top.ngd		Top.ngd
Top.ngr		Top.ngr
Top.pad		Top.pad
Top.par		Top.par
Top.pcf		Top.pcf
Top.prj		Top.prj
Top.ptwx		Top.ptwx