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pulp-platform/redundancy_cells
pulp-platform/redundancy_cells PublicSystemVerilog IPs and Modules for architectural redundancy designs.
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pulp-platform/bender
pulp-platform/bender PublicA dependency management tool for hardware projects.
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pulp-platform/pulp
pulp-platform/pulp PublicThis is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
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pulp-platform/axi
pulp-platform/axi PublicAXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
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pulp-platform/iDMA
pulp-platform/iDMA PublicA modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
-
pulp-platform/FlooNoC
pulp-platform/FlooNoC PublicA Fast, Low-Overhead On-chip Network
Navigation Menu
Highlights
- Pro
Pinned Loading
-
pulp-platform/redundancy_cells
pulp-platform/redundancy_cells PublicSystemVerilog IPs and Modules for architectural redundancy designs.
-
pulp-platform/bender
pulp-platform/bender PublicA dependency management tool for hardware projects.
-
pulp-platform/pulp
pulp-platform/pulp PublicThis is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
-
pulp-platform/axi
pulp-platform/axi PublicAXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
-
pulp-platform/iDMA
pulp-platform/iDMA PublicA modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
-
pulp-platform/FlooNoC
pulp-platform/FlooNoC PublicA Fast, Low-Overhead On-chip Network
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