[0051] Reduce to AlignedLoad and AlignedStore operations

[mapodaca-nv]

This version just contains the AlignedLoad and AlignedStore operations, using absolute alignments.

This version greatly simplifies the proposal by removing the BaseAlignment attribute and other related changes.

Based on feedback from @tex3d in #720

Also, fixed minor formatting issues.

[mapodaca-nv]

See Implement ByteAddressBuffer AlignedLoad and AlignedStore operations #7993

[jenatali]

Is there any adjustment to bounds checking behavior here? For raw buffers bound as root SRV/UAV, there are no bounds to check, so specifying larger alignments can vectorize without issue, but for descriptor-backed SRV/UAV where the bounds themselves have 16-byte alignment, it seems difficult to take advantage of alignments larger than 16, since that's the granularity where bounds checks have to be inserted.

[mapodaca-nv]

Is there any adjustment to bounds checking behavior here? For raw buffers bound as root SRV/UAV, there are no bounds to check, so specifying larger alignments can vectorize without issue, but for descriptor-backed SRV/UAV where the bounds themselves have 16-byte alignment, it seems difficult to take advantage of alignments larger than 16, since that's the granularity where bounds checks have to be inserted.

For descriptor-based views, the minimum alignment for the base address is 16 bytes. The shader-based alignment specifies the absolute alignment of the effective address (base + offset), which could be smaller or larger than the base alignment. The backend compiler could still take advantage of the knowledge that descriptor-based views have a 16 byte minimum base address alignment, unlike root views, as they do today. As far as bounds checking itself, unless I'm missing something, this should have no impact on the expected behavior.

[jenatali]

Oh, you're right, there's not a 16-byte size-alignment requirement for descriptors, only for the base offset, nevermind.