Skip to content
View mrgreenapple24's full-sized avatar
💭
Fixing Errors
💭
Fixing Errors
  • Goa
  • 11:29 (UTC +05:30)

Block or report mrgreenapple24

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
mrgreenapple24/README.md

Typing SVG

I’m a developer deeply interested in the intersection of software and silicon. From building physics engines in C++ to designing processors in Verilog, I love tearing down abstractions to see how things work under the hood.

Support:

ko-fi.com/mrgreenapple24



Pinned Loading

  1. DCT-HDL DCT-HDL Public

    A hardware implementation for the algebraic fast DCT-2 Algorithm

    Verilog

  2. RvNOVA RvNOVA Public

    Risc-V CPU Design in Verilog

    Verilog 1

  3. chessNova chessNova Public

    C 1 2

  4. Devsoc-BPGC/ElysiumEngine Devsoc-BPGC/ElysiumEngine Public

    C++ 2