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Update README.md #6

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14 changes: 13 additions & 1 deletion README.md
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Expand Up @@ -35,16 +35,28 @@ Hardware – PCs, Cyclone II , USB flasher

/* Program to implement the given logic function and to verify its operations in quartus using Verilog programming.

Developed by: RegisterNumber:*/
Developed by:VIGNESH V
RegisterNumber:24900753*/


**RTL realization**
![de22 project diagrsm](https://github.com/user-attachments/assets/206510c2-3e92-4ee6-8c5e-e5134302beca)


![WhatsApp Image 2024-11-26 at 11 49 30_2fb98d4f](https://github.com/user-attachments/assets/c4570773-8cbc-42d2-bda2-b416b0a5a8c1)



**Output:**

**RTL**

**Timing Diagram**
![WhatsApp Image 2024-11-26 at 11 49 31_330cd36f](https://github.com/user-attachments/assets/518e27eb-b2b0-4ffd-acb9-8a913d217633)


![WhatsApp Image 2024-11-26 at 11 49 31_5fdfd8d2](https://github.com/user-attachments/assets/d232c584-94a2-4c34-a4ff-79e047c026ce)


**Result:**

Expand Down