riscv-debug-bridge

Implements (work in progress) parts of the RISC-V Debug Specification, including the Debug Transport Hardware (JTAG), Debug Transport Module and Debug Module. DM and DTM communicate via a simple handshaking protocol as defined in the spec.

Getting started

We are going to launch 3 different processes:

1.

We have to launch the Debug Transport Hardware which communicates via the bitbang protocol (over network sockets) with openocd.

The following command launches the the jtag modules which opens and listens on port 9842:

$ python3 jtag_dtm.py

2.

$ openocd -f sail.cfg

Or optional to enable debugging:

$ openocd -f sail.cfg -d

3.

$ telnet localhost 4444