ici/crc: add x86 SSE4.2 + PCLMULQDQ hardware acceleration for BPv7/CFDP CRCs - #112
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ici/crc: add x86 SSE4.2 + PCLMULQDQ hardware acceleration for BPv7/CFDP CRCs#112zebastian wants to merge 1 commit into
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…DP CRCs Accelerate the two CRC polynomials on the ION data path with x86 intrinsics, selected at run time so a single binary still runs on CPUs that lack the instructions: - CRC-32C (poly 0x1EDC6F41): use the SSE4.2 crc32 instruction, which computes exactly this reflected polynomial. Wired into both ion_CRC32_1EDC6F41_C and ion_CRC32_1EDC6F41_C_slice (BPv7 block CRCs, CFDP checksums). ~2.2x over the slice-by-16 table. - CRC-16/X-25 (poly 0x1021): no dedicated instruction exists, so fold 16-byte blocks with PCLMULQDQ carry-less multiply and reduce the result with the byte-wise table. Fold constants reflect(x^143 mod P) and reflect(x^79 mod P). ~2.6x over the slice-by-8 table. Detection is via __builtin_cpu_supports(); each accelerated routine carries a per-function target attribute so the rest of the object stays at the baseline ISA (no -msse4.2/-mpclmul build flags, no SIGILL on older CPUs). Output is bitwise-identical to the existing table routines, verified exhaustively across all offsets, lengths, and accumulation boundaries. Guarded to x86/x86_64 GCC/Clang; other polynomials and platforms fall through to the table paths unchanged.
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Accelerate the two CRC polynomials on the ION data path with x86 intrinsics, selected at run time so a single binary still runs on CPUs that lack the instructions:
CRC-32C (poly 0x1EDC6F41): use the SSE4.2 crc32 instruction, which computes exactly this reflected polynomial. Wired into both ion_CRC32_1EDC6F41_C and ion_CRC32_1EDC6F41_C_slice (BPv7 block CRCs, CFDP checksums). ~2.2x over the slice-by-16 table.
CRC-16/X-25 (poly 0x1021): no dedicated instruction exists, so fold 16-byte blocks with PCLMULQDQ carry-less multiply and reduce the result with the byte-wise table. Fold constants reflect(x^143 mod P) and reflect(x^79 mod P). ~2.6x over the slice-by-8 table.
Detection is via __builtin_cpu_supports(); each accelerated routine carries a per-function target attribute so the rest of the object stays at the baseline ISA (no -msse4.2/-mpclmul build flags, no SIGILL on older CPUs). Output is bitwise-identical to the existing table routines, verified exhaustively across all offsets, lengths, and accumulation boundaries. Guarded to x86/x86_64 GCC/Clang; other polynomials and platforms fall through to the table paths unchanged.
CRC16 PCLMULQDQ: 9.20 GB/s vs 3.51 GB/s slice-by-8 table (~2.6×)
CRC32 SSE4.2: 10.87 GB/s vs. 4.86 GB/s for the existing slice-by-16 table (~2.2×)