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Parse ANSI parameters declaration #1160

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Parse ANSI parameters declaration #1160

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364b6aa
Add ansi parameters list parsing
Feb 11, 2025
c9c7a97
Add ansi parameters list test
Feb 11, 2025
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1 change: 1 addition & 0 deletions src/lexer.l
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Original file line number Diff line number Diff line change
Expand Up @@ -505,6 +505,7 @@ BEFORE ?i:before
<UDP>{UDP_EDGE} { yylval.i64 = yytext[0]; return tUDPEDGE; }
<UDP>{UDP_INDICATOR} { yylval.str = xstrdup(yytext); return tUDPIND; }

<*>"#(" { TOKEN(tHASHLPAREN); }
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I don't think #( is a single token. It's shown with a space between it them the grammar in the standard (e.g. page 1138 of 1800-2017) and also here:

https://www.sigasi.com/tech/systemverilog.ebnf/#module-parameters-and-ports

Icarus Verilog and Verilator also both treat the # and ( as separate tokens.

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Ok thanks for the review I wasn't aware that they were separate tokens, I'll try to look better into the syntax and adjust the code. It's gonna take a bit of time though

<*>"(" { TOKEN(tLPAREN); }
<*>")" { TOKEN(tRPAREN); }
<*>"[" { TOKEN(tLSQUARE); }
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2 changes: 1 addition & 1 deletion src/scan.c
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Expand Up @@ -264,7 +264,7 @@ const char *token_str(token_t tok)
"endtask", "endfunction", "`begin_keywords", "`end_keywords", "real",
"shortreal", "realtime", "`__nvc_push", "`__nvc_pop", "++", "--",
"var", "`default_nettype", "tri", "tri0", "tri1", "wand", "triand",
"wor", "trior", "trireg", "uwire", "none",
"wor", "trior", "trireg", "uwire", "none", "#("
};

if (tok >= 200 && tok - 200 < ARRAY_LEN(token_strs))
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1 change: 1 addition & 0 deletions src/scan.h
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Expand Up @@ -436,5 +436,6 @@ void reset_sdf_parser(void);
#define tTRIREG 535
#define tUWIRE 536
#define tNONE 537
#define tHASHLPAREN 538

#endif // _SCAN_H
30 changes: 30 additions & 0 deletions src/vlog/vlog-parse.c
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Expand Up @@ -3260,6 +3260,33 @@ static void p_list_of_port_declarations(vlog_node_t mod)
consume(tRPAREN);
}

static void p_ansi_parameter_declaration(vlog_node_t mod)
{
// parameter data_type_or_implicit parameter_assigment

BEGIN("ANSI parameter declaration");

consume(tPARAMETER);

vlog_node_t dt = p_data_type_or_implicit();
vlog_add_decl(mod, p_param_assignment(dt));
}

static void p_list_of_param_declarations(vlog_node_t mod)
{
// parameter_port_list ::= ansi_param_assignments { , ansi_param_assignments }
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I'm using the System Verilog grammar rather than the traditional Verilog one


BEGIN("list of parameter declarations");

consume(tHASHLPAREN);

do {
p_ansi_parameter_declaration(mod);
} while (optional(tCOMMA));

consume(tRPAREN);
}

static void p_module_ansi_header(vlog_node_t mod)
{
// { attribute_instance } module_keyword [ lifetime ] module_identifier
Expand All @@ -3268,6 +3295,9 @@ static void p_module_ansi_header(vlog_node_t mod)

EXTEND("module ANSI header");

if (peek() == tHASHLPAREN)
p_list_of_param_declarations(mod);

if (peek() == tLPAREN)
p_list_of_port_declarations(mod);

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23 changes: 23 additions & 0 deletions test/test_vlog.c
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Expand Up @@ -631,6 +631,28 @@ START_TEST(test_param1)
}
END_TEST

START_TEST(test_param2)
{
input_from_file(TESTDIR "/vlog/param2.v");

const error_t expect[] = {
{ 6, "duplicate declaration" },
{ -1, NULL }
};
expect_errors(expect);

vlog_node_t m = vlog_parse();
fail_if(m == NULL);
fail_unless(vlog_kind(m) == V_MODULE);

vlog_check(m);

fail_unless(vlog_parse() == NULL);

check_expected_errors();
}
END_TEST

START_TEST(test_pp3)
{
input_from_file(TESTDIR "/vlog/pp3.v");
Expand Down Expand Up @@ -758,6 +780,7 @@ Suite *get_vlog_tests(void)
tcase_add_test(tc, test_enum1);
tcase_add_test(tc, test_union1);
tcase_add_test(tc, test_param1);
tcase_add_test(tc, test_param2);
tcase_add_test(tc, test_pp3);
tcase_add_test(tc, test_concat1);
tcase_add_test(tc, test_pp4);
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7 changes: 7 additions & 0 deletions test/vlog/param2.v
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Original file line number Diff line number Diff line change
@@ -0,0 +1,7 @@
module param2 #(
parameter [7:0] p1 = 8'd5,
parameter p2 = 8
);
assign w1 = p1; // OK
parameter logic p1 = 1; // Error
endmodule // param2
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