DDR3 UART Loopback Controller

Small FPGA design that writes data from UART into DDR3 via AXI and then reads it back to the PC, acting as a simple end‑to‑end loopback and throughput tester.

System overview

Main datapath (FPGA/fpga_test.v):

UART RX → Async FIFO → AXI DDR3 Write/Read → Async FIFO → UART TX

• Word size: 32 bytes (256‑bit) per DDR beat
• Goal: Prove that the full UART → DDR3 → UART loopback works correctly and measure sustained throughput.

Minimal specifications

• FPGA: Efinix (generic AXI‑based DDR3 interface)
• AXI data width: 256‑bit
• UART: 115200 baud, 8‑N‑1 (parameterizable in uart_rx.v / uart_tx.v)
• Clocks (example):
  • axi_clk: DDR user clock
  • uart_clk: 50 MHz UART/logic clock

Main RTL blocks (only the essentials)

• FPGA/fpga_test.v (top) – Connects UART, two simple_async_fifo instances, axi_ctrl, DDR3 ports and debug LEDs.
  • debug_led[0]: heartbeat (AXI clock alive)
  • debug_led[1]: ddr_init_done
  • debug_led[2]: FIFO overflow (uplink or downlink)
  • debug_led[3]: AXI app reset de‑asserted
• rtl/axi_ctrl.v – Simple AXI master that writes all incoming 256‑bit words to DDR, then reads them back into the downlink FIFO.
• rtl/simple_async_fifo.v – Dual‑clock FIFO bridging UART and AXI domains.
• rtl/uart_rx.v / rtl/uart_tx.v – UART front‑end with basic RX/TX state machines.
• rtl/ddr_reset_sequencer.v – DDR reset and initialization timing.

Running the full loopback from the PC

1. Program the FPGA with a bitstream that instantiates top from FPGA/fpga_test.v and connects DDR3 + UART pins.
2. Install Python requirement:

   pip install pyserial

3. Edit scripts/test.py to match your serial port:

   PORT = "/dev/ttyUSB1"   # set to your board's UART port
   BAUD = 115200

4. Start the tester:

   python scripts/test.py

5. Use the menu for:
   • Single 32‑byte packet loopback
   • Multiple packets
   • Throughput benchmark (default 200 KB)

The loopback is considered working properly when the script prints “Data verification: PASSED ✓” for the selected test (bytes sent = bytes received and contents match).

Extras

• tb/tb.v – Verilog testbench that drives UART traffic into the top‑level loopback.
• rtl/uart_fifo_uart_top.v – Standalone UART + FIFO demo (no DDR), useful for quick bring‑up.