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1. riscv-soc-integration riscv-soc-integration Public

   Synthesizable Single-Cycle RISC-V SoC featuring an APB v3.0 Bridge, UART Controller, and hardware flow control. Designed in Verilog.

   Verilog 9

2. project-vajra project-vajra Public

   Project Vajra is a custom-designed, 32-bit, 5-stage pipelined RISC-V microprocessor architecture. It has been successfully synthesized, floorplanned, and routed down to the physical GDSII layout us…

   Verilog 4

3. Vajra-core Vajra-core Public

   Open-source RISC-V computing platform exploring processor design, hardware acceleration, edge AI, FPGA prototyping, and future ASIC implementation.

   Verilog 2 1

4. RISCV-5-Stage-Pipelined-Processor RISCV-5-Stage-Pipelined-Processor Public

   32-bit RISC-V CPU with 5-stage pipeline and Hazard Forwarding Unit

   Verilog 1 1

5. RISCV_Single_Cycle_Processor RISCV_Single_Cycle_Processor Public

   A Verilog implementation of a 32-bit RISC-V CPU

   Verilog

6. amba-apb-master amba-apb-master Public

   A synthesizable, standard-compliant AMBA APB v3.0 Master Bridge IP Core in Verilog, featuring FSM-based control and wait-state management for RISC-V SoC integration.

   SystemVerilog