High-Frequency Trading (HFT) Engineer | Low-Latency Systems | C++ | Market Microstructure
I design and optimize ultra-low latency trading systems with a focus on performance engineering, deterministic systems, and hardware-aware design.
- Low-Latency C++ (C++17/20)
- HFT System Architecture (Feed Handlers, Order Books, Execution Engines)
- Market Microstructure & Exchange Mechanics
- Lock-Free & Cache-Friendly Data Structures
- NUMA, CPU Pinning, Context Switch Reduction
- Linux Performance Profiling (perf, valgrind, flamegraphs)
- Building production-grade HFT infrastructure from scratch
- Exchange protocol parsing & binary feed handlers
- Latency measurement & jitter analysis frameworks
- Preparation for top-tier HFT / Quant Dev roles
- Zero-copy packet processing
- Deterministic latency tracking
- Cache-line aligned data paths
- O(1) order updates
- Exchange-style matching logic
- Memory-pool–based allocation
- Market replay engine
- Strategy backtesting
- Slippage & latency modeling
Languages
C++ Python Shell
Systems & Tools
Linux GCC Clang GDB Perf Valgrind
Concepts
Lock-Free Programming NUMA CPU Affinity Latency Engineering
“In HFT, performance is not optimized — it is engineered.”
I believe in first-principles thinking, mechanical sympathy, and correctness before abstraction.