samples: matter: Add support for non-PM builds (excluding nrf5340/nrf9160)

applications/image_flasher/CMakeLists.txt

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+#
+# Copyright (c) 2025 Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+#
+
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr
+  COMPONENTS zephyr_default:boards
+  REQUIRED HINTS $ENV{ZEPHYR_BASE}
+)
+
+project(image_flasher)
+
+# Create the runners_yaml_props_target that flash system expects
+add_custom_target(runners_yaml_props_target)
+
+# Fetch hex file to flash from sysbuild
+zephyr_get(hex_file_to_flash SYSBUILD LOCAL VAR HEX_FILE)
+zephyr_get(default_image SYSBUILD GLOBAL VAR IMAGE_FLASHER_DEFAULT_IMAGE)
+
+# Set hex_file property to point to the hex file
+set_target_properties(runners_yaml_props_target PROPERTIES
+  hex_file "${hex_file_to_flash}"
+)
+
+# Override the runners.yaml path to use CMAKE_CURRENT_BINARY_DIR/zephyr instead of
+# PROJECT_BINARY_DIR, this ensures runners.yaml is generated at <build>/softdevice/zephyr where
+# west expects it
+set(PROJECT_BINARY_DIR ${CMAKE_CURRENT_BINARY_DIR}/zephyr)
+
+# Copy over Kconfig and dts files from the main image
+set(default_image_binary_dir ${PROJECT_BINARY_DIR}/../../${default_image}/zephyr)
+zephyr_file_copy(${default_image_binary_dir}/.config ${PROJECT_BINARY_DIR}/.config ONLY_IF_DIFFERENT)
+zephyr_file_copy(${default_image_binary_dir}/edt.pickle ${PROJECT_BINARY_DIR}/edt.pickle ONLY_IF_DIFFERENT)
+import_kconfig(CONFIG_ ${default_image_binary_dir}/.config)
+
+# Manually include board configuration to enable automatic runners.yaml generation
+foreach(dir ${BOARD_DIRECTORIES})
+  include(${dir}/board.cmake OPTIONAL)
+endforeach()
+
+# Include flash support to automatically generate runners.yaml
+include(${ZEPHYR_BASE}/cmake/flash/CMakeLists.txt)
+
+# Silent unused variable warnings
+set(EXTRA_KCONFIG_TARGETS)
+set(FORCED_CONF_FILE)

dts/samples/matter/nrf52840dk_nrf52840_partitions.dtsi

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+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+/delete-node/ &boot_partition;
+/delete-node/ &slot0_partition;
+/delete-node/ &slot1_partition;
+/delete-node/ &storage_partition;
+
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x00000000 0x00007000>;
+		};
+
+		slot0_partition: partition@7000 {
+			label = "image-0";
+			reg = <0x00007000 0x000f0000>;
+		};
+
+		factory_data_partition: partition@f7000 {
+			label = "factory-data";
+			reg = <0x000f7000 0x00001000>;
+		};
+
+		storage_partition: partition@f8000 {
+			label = "storage";
+			reg = <0x000f8000 0x00008000>;
+		};
+	};
+};
+
+&mx25r64 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		slot1_partition: partition@0 {
+			label = "image-1";
+			reg = <0x00000000 0x000f0000>;
+		};
+	};
+};

dts/samples/matter/nrf54l15dk_nrf54l10_cpuapp_partitions.dtsi

@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+/delete-node/ &boot_partition;
+/delete-node/ &slot0_partition;
+/delete-node/ &slot1_partition;
+/delete-node/ &storage_partition;
+
+&cpuapp_rram {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x00000000 0x0000d000>;
+		};
+
+		slot0_partition: partition@d000 {
+			label = "image-0";
+			reg = <0x0000d000 0x000e5000>;
+		};
+
+		factory_data_partition: partition@f2000 {
+			label = "factory-data";
+			reg = <0x000f2000 0x00001000>;
+		};
+
+		storage_partition: partition@f3000 {
+			label = "storage";
+			reg = <0x000f3000 0x0000a000>;
+		};
+	};
+};
+
+&mx25r64 {
+	status = "okay";
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		slot1_partition: partition@0 {
+			label = "image-1";
+			reg = <0x00000000 0x000e5000>;
+		};
+	};
+};
+
+/* restore full SRAM space - by default some parts are dedicated to FLRP */
+&cpuapp_sram {
+	reg = <0x20000000 DT_SIZE_K(192)>;
+	ranges = <0x0 0x20000000 DT_SIZE_K(192)>;
+};

dts/samples/matter/nrf54l15dk_nrf54l15_cpuapp_internal_partitions.dtsi

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+/delete-node/ &boot_partition;
+/delete-node/ &slot0_partition;
+/delete-node/ &slot1_partition;
+/delete-node/ &storage_partition;
+
+/* restore full RRAM and SRAM space - by default some parts are dedicated to FLRP */
+&cpuapp_rram {
+	reg = <0x0 DT_SIZE_K(1524)>;
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x00000000 0x0000d000>;
+		};
+
+		slot0_partition: partition@d000 {
+			label = "image-0";
+			reg = <0x0000d000 0x000d8000>;
+		};
+
+		/* Compression ratio 34.75% */
+		slot1_partition: partition@E5000 {
+			label = "image-1";
+			reg = <0x00e5000 0x0008d000>;
+		};
+
+		factory_data_partition: partition@172000 {
+			label = "factory-data";
+			reg = <0x00172000 0x00001000>;
+		};
+
+		storage_partition: partition@173000 {
+			label = "storage";
+			reg = <0x00173000 0x0000a000>;
+		};
+	};
+};
+
+&mx25r64 {
+	status = "disabled";
+};
+
+&cpuapp_sram {
+	reg = <0x20000000 DT_SIZE_K(256)>;
+	ranges = <0x0 0x20000000 DT_SIZE_K(256)>;
+};

dts/samples/matter/nrf54l15dk_nrf54l15_cpuapp_partitions.dtsi

@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+/delete-node/ &boot_partition;
+/delete-node/ &slot0_partition;
+/delete-node/ &slot1_partition;
+/delete-node/ &storage_partition;
+
+/* restore full RRAM and SRAM space - by default some parts are dedicated to FLRP */
+&cpuapp_rram {
+	reg = <0x0 DT_SIZE_K(1524)>;
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x00000000 0x0000d000>;
+		};
+
+		slot0_partition: partition@d000 {
+			label = "image-0";
+			reg = <0x0000d000 0x00165000>;
+		};
+
+		factory_data_partition: partition@172000 {
+			label = "factory-data";
+			reg = <0x00172000 0x00001000>;
+		};
+
+		storage_partition: partition@173000 {
+			label = "storage";
+			reg = <0x00173000 0x0000a000>;
+		};
+	};
+};
+
+&mx25r64 {
+	status = "okay";
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		slot1_partition: partition@0 {
+			label = "image-1";
+			reg = <0x00000000 0x00165000>;
+		};
+	};
+};
+
+&cpuapp_sram {
+	reg = <0x20000000 DT_SIZE_K(256)>;
+	ranges = <0x0 0x20000000 DT_SIZE_K(256)>;
+};

dts/samples/matter/nrf54lm20dk_nrf54lm20a_cpuapp_internal_partitions.dtsi

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+/delete-node/ &boot_partition;
+/delete-node/ &slot0_partition;
+/delete-node/ &slot1_partition;
+/delete-node/ &storage_partition;
+
+/* restore full RRAM and SRAM space - by default some parts are dedicated to FLRP */
+&cpuapp_rram {
+	reg = <0x0 DT_SIZE_K(2036)>;
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x00000000 0x0000a000>;
+		};
+
+		slot0_partition: partition@a000 {
+			label = "image-0";
+			reg = <0x0000a000 0x00126000>;
+		};
+
+		/* Compression ratio 34.75% */
+		slot1_partition: partition@130000 {
+			label = "image-1";
+			reg = <0x00130000 0x000c0000>;
+		};
+
+		factory_data_partition: partition@1f0000 {
+			label = "factory-data";
+			reg = <0x001f0000 0x00001000>;
+		};
+
+		storage_partition: partition@1f1000 {
+			label = "storage";
+			reg = <0x001f1000 0x0000c000>;
+		};
+	};
+};
+
+&mx25r64 {
+	status = "disabled";
+};
+
+&cpuapp_sram {
+	reg = <0x20000000 DT_SIZE_K(511)>;
+	ranges = <0x0 0x20000000 DT_SIZE_K(511)>;
+};

dts/samples/matter/nrf54lm20dk_nrf54lm20a_cpuapp_partitions.dtsi

@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+/delete-node/ &boot_partition;
+/delete-node/ &slot0_partition;
+/delete-node/ &slot1_partition;
+/delete-node/ &storage_partition;
+
+/* restore full RRAM and SRAM space - by default some parts are dedicated to FLRP */
+&cpuapp_rram {
+	reg = <0x0 DT_SIZE_K(2036)>;
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x00000000 0x0000d000>;
+		};
+
+		slot0_partition: partition@d000 {
+			label = "image-0";
+			reg = <0x0000d000 0x001e3000>;
+		};
+
+		factory_data_partition: partition@1f0000 {
+			label = "factory-data";
+			reg = <0x001f0000 0x00001000>;
+		};
+
+		storage_partition: partition@1f1000 {
+			label = "storage";
+			reg = <0x001f1000 0x0000c000>;
+		};
+	};
+};
+
+&mx25r64 {
+	status = "okay";
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		slot1_partition: partition@0 {
+			label = "image-1";
+			reg = <0x00000000 0x001e3000>;
+		};
+	};
+};
+
+&cpuapp_sram {
+	reg = <0x20000000 DT_SIZE_K(511)>;
+	ranges = <0x0 0x20000000 DT_SIZE_K(511)>;
+};