Skip to content

nRF Desktop: nRF54LM20: execute the app code from RAM #25661

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 4 commits into from
Nov 27, 2025
+868 −60
Merged

nRF Desktop: nRF54LM20: execute the app code from RAM #25661

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
4 commits
Select commit Hold shift + click to select a range
02e3019
applications: nrf_desktop: dfu_mcumgr: align mcuboot modes
kapi-no Nov 26, 2025
cb7e64d
applications: nrf_desktop: dfu: add support for MCUboot RAM load
kapi-no Nov 26, 2025
5d34ecb
applications: nrf_desktop: add constraints for MCUboot RAM load
kapi-no Nov 26, 2025
19ba58a
applications: nrf_desktop: nrf54lm20dk: support USB 8k report rate
kapi-no Nov 26, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
49 changes: 49 additions & 0 deletions applications/nrf_desktop/CMakeLists.txt
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -47,6 +47,55 @@ if(CONFIG_IMG_MANAGER)
zephyr_library_link_libraries(MCUBOOT_BOOTUTIL)
endif()

if(CONFIG_BOOTLOADER_MCUBOOT)
if(NOT (CONFIG_MCUBOOT_BOOTLOADER_MODE_SINGLE_APP OR
CONFIG_MCUBOOT_BOOTLOADER_MODE_DIRECT_XIP OR
Copy link
Contributor

@MarekPieta MarekPieta Nov 26, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

mcuboot_qspi configuration of nrf52840dk uses MCUboot with swap (CONFIG_MCUBOOT_BOOTLOADER_MODE_SWAP_USING_MOVE). It triggers the warning here (false positive).

Copy link
Contributor

@MarekPieta MarekPieta Nov 27, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

btw. What do you think about enabling it explicitly to prevent breaking backwards compatibility if the default changes in scope of NCS?

CONFIG_MCUBOOT_BOOTLOADER_MODE_RAM_LOAD OR
CONFIG_MCUBOOT_BOOTLOADER_MODE_SWAP_USING_MOVE))
message(WARNING "
------------------------------------------------------------------------------
--- WARNING: The currently selected mode of the MCUboot bootloader has not ---
--- been used or tested with any nRF Desktop configuration. ---
------------------------------------------------------------------------------
")
endif()

if(CONFIG_MCUBOOT_BOOTLOADER_MODE_RAM_LOAD)
message(WARNING "
-----------------------------------------------------------------------------
--- WARNING: The RAM load mode of the MCUboot bootloader is experimental. ---
-----------------------------------------------------------------------------
")

# Enforce the specific RAM layout in DTS when MCUboot uses the RAM load mode.
dt_nodelabel(app_rxm_region_node NODELABEL cpuapp_sram_app_rxm_region)
if(NOT app_rxm_region_node)
message(FATAL_ERROR
"Missing RXM (ROM + RAM) region definition (cpuapp_sram_app_rxm_region) for the "
"application image in DTS.")
endif()

dt_nodelabel(mcuboot_ram_region_node NODELABEL cpuapp_sram_mcuboot_ram_region)
if(NOT mcuboot_ram_region_node)
message(FATAL_ERROR
"Missing RAM region definition (cpuapp_sram_mcuboot_ram_region) for the MCUboot "
"bootloader in DTS.")
endif()

dt_reg_addr(app_rxm_region_addr PATH ${app_rxm_region_node})
dt_reg_addr(mcuboot_ram_region_addr PATH ${mcuboot_ram_region_node})
if(mcuboot_ram_region_addr LESS_EQUAL app_rxm_region_addr)
message(FATAL_ERROR
"The start address of the RXM region (0x${app_rxm_region_addr}) must be located "
Copy link
Contributor

@MarekPieta MarekPieta Nov 27, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Consider mentioning that it's an app-specific assumption (not a generic one). Maybe something similar to:

The validation process assumes a specific RAM layout in DTS - you can refer to the following file as an example: ./configuration/nrf54lm20dk_nrf54lm20a_cpuapp/memory_map_ram_load.dtsi

"before the start address of the MCUboot RAM region (0x${mcuboot_ram_region_addr})."
"The current order is wrong — modify your DTS RAM layout to fix this error.")
endif()

# Ensure that generated application image will fit in the defined RAM partition after build.
zephyr_linker_sources(RODATA linker/mcuboot_ram_load.ld)
endif()
endif()

if(CONFIG_DESKTOP_CONFIG_CHANNEL_ENABLE)
zephyr_linker_sources(SECTIONS nrf_desktop.ld)
zephyr_linker_section(NAME config_channel_modules KVMA RAM_REGION GROUP RODATA_REGION NOINPUT)
Expand Down
12 changes: 12 additions & 0 deletions applications/nrf_desktop/Kconfig.defaults
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -24,6 +24,18 @@ config DESKTOP_LTO_DEFAULTS
help
nRF Desktop enables LTO to limit memory usage and improve performance.

config DESKTOP_MCUBOOT_RAM_LOAD_MCUBOOT_RAM_START_ADDR
hex
depends on MCUBOOT_BOOTLOADER_MODE_RAM_LOAD
depends on $(dt_nodelabel_exists,cpuapp_sram_mcuboot_ram_region)
default $(dt_nodelabel_reg_addr_hex,cpuapp_sram_mcuboot_ram_region)
Comment on lines +30 to +31
Copy link
Contributor

@tejlmand tejlmand Nov 27, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

we start to have several devicetree labels trying to achieve similar thing, which is to have the code executed / placed at a specific location.

Until we have some more common way to achieve this on higher level, then I would like to know why the existing CONFIG_SRAM_OFFSET is not suitable in this particular case for the MCUboot build ?

@nordicjm please have a look at this, and do some thinking regarding devicetree node used for features like this one, as well as the multicore TCM etc.
Other places of interest: zephyrproject-rtos/zephyr#91591 github.com//pull/25737

Not blocking comment for this PR, due to closeness to rc, but be prepared for follow-up work in this area.

Copy link
Contributor Author

@kapi-no kapi-no Nov 27, 2025 •
edited
Loading

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This Kconfig option is only used in the context of the following linker script:

applications/nrf_desktop/linker/mcuboot_ram_load.ld

If set correctly, the CONFIG_SRAM_OFFSET would work in the context of the MCUboot image. However, in the MCUboot image context, we do not have access to the __rom_region_end symbol of the application image.

Also, you cannot change the CONFIG_SRAM_OFFSET Kconfig option from the default non-zero value using the standard *.conf file, as this is a promptless option. It is difficult to set this option correctly for the MCUboot at the nRF Desktop project level (you would have to force it via sysbuild)

Copy link
Contributor

@tejlmand tejlmand Nov 27, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Thanks for the extra details.

Will be good to keep in mind when trying to find a better, more consistent / uniform solution for a recurrent problem on more advanced SoCs.

help
The start address of the MCUboot RAM region. The Kconfig option is used to validate
if the executable RAM region of the application image (also called the ROM section)
does not overlap with the RAM region of the MCUboot image. The validation process
assumes a specific RAM layout in DTS - you can refer to the following file as an example:
./configuration/nrf54lm20dk_nrf54lm20a_cpuapp/memory_map_ram_load.dtsi

config APP_EVENT_MANAGER_MAX_EVENT_CNT
default 64
help
Expand Down
5 changes: 5 additions & 0 deletions applications/nrf_desktop/configuration/nrf54lm20dk_nrf54lm20a_cpuapp/app.overlay
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -6,6 +6,11 @@

#include "app_common.dtsi"

/* Application does not use cpuflpr core. Assign whole RRAM to cpuapp. */
&cpuapp_rram {
reg = < 0x0 DT_SIZE_K(2036) >;
};

/ {
hid_dev_0: hid_dev_0 {
compatible = "zephyr,hid-device";
Expand Down
5 changes: 0 additions & 5 deletions applications/nrf_desktop/configuration/nrf54lm20dk_nrf54lm20a_cpuapp/app_common.dtsi
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -4,11 +4,6 @@
* SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
*/

/* Application does not use cpuflpr core. Assign whole RRAM to cpuapp. */
&cpuapp_rram {
reg = < 0x0 DT_SIZE_K(2036) >;
};

/ {
/* Disable pwmleds and redefine them to align configuration with CAF LEDs requirements. */
/delete-node/ pwmleds;
Expand Down
5 changes: 5 additions & 0 deletions applications/nrf_desktop/configuration/nrf54lm20dk_nrf54lm20a_cpuapp/app_llvm.overlay
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -6,6 +6,11 @@

#include "app_common.dtsi"

/* Application does not use cpuflpr core. Assign whole RRAM to cpuapp. */
&cpuapp_rram {
reg = < 0x0 DT_SIZE_K(2036) >;
};

/ {
hid_dev_0: hid_dev_0 {
compatible = "zephyr,hid-device";
Expand Down
25 changes: 25 additions & 0 deletions applications/nrf_desktop/configuration/nrf54lm20dk_nrf54lm20a_cpuapp/app_ram_load.overlay
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,25 @@
/*
* Copyright (c) 2025 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
*/

#include "app_common.dtsi"
#include "memory_map_ram_load.dtsi"

/ {
chosen {
/* We need to point where we want to place the retained memory region that
* is shared with the MCUboot bootloader image and contains the image metadata.
*/
zephyr,bootloader-info = &boot_info0;
};

hid_dev_0: hid_dev_0 {
compatible = "zephyr,hid-device";
label = "HID0";
protocol-code = "mouse";
in-polling-period-us = <125>;
in-report-size = <64>;
};
};
5 changes: 5 additions & 0 deletions applications/nrf_desktop/configuration/nrf54lm20dk_nrf54lm20a_cpuapp/app_release.overlay
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -6,6 +6,11 @@

#include "app_common.dtsi"

/* Application does not use cpuflpr core. Assign whole RRAM to cpuapp. */
&cpuapp_rram {
reg = < 0x0 DT_SIZE_K(2036) >;
};

/ {
hid_dev_0: hid_dev_0 {
compatible = "zephyr,hid-device";
Expand Down
30 changes: 30 additions & 0 deletions ...ions/nrf_desktop/configuration/nrf54lm20dk_nrf54lm20a_cpuapp/app_release_ram_load.overlay
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,30 @@
/*
* Copyright (c) 2025 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
*/

#include "app_common.dtsi"
#include "memory_map_ram_load.dtsi"

/ {
chosen {
/* We need to point where we want to place the retained memory region that
* is shared with the MCUboot bootloader image and contains the image metadata.
*/
zephyr,bootloader-info = &boot_info0;
};

hid_dev_0: hid_dev_0 {
compatible = "zephyr,hid-device";
label = "HID0";
protocol-code = "mouse";
in-polling-period-us = <125>;
in-report-size = <64>;
};
};

/* For nRF54L, watchdog status is disabled by default. Needs to be enabled in DTS overlay. */
&wdt31 {
status = "okay";
};
10 changes: 10 additions & 0 deletions ...s/nrf_desktop/configuration/nrf54lm20dk_nrf54lm20a_cpuapp/images/mcuboot/app_llvm.overlay
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,10 @@
/*
* Copyright (c) 2025 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
*/

/* Application does not use cpuflpr core. Assign whole RRAM to cpuapp. */
&cpuapp_rram {
reg = < 0x0 DT_SIZE_K(2036) >;
};
20 changes: 20 additions & 0 deletions ...f_desktop/configuration/nrf54lm20dk_nrf54lm20a_cpuapp/images/mcuboot/app_ram_load.overlay
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,20 @@
/*
* Copyright (c) 2025 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
*/

#include "../../memory_map_ram_load.dtsi"

/ {
chosen {
/* We need to point where we want to place MCUboot code. */
zephyr,code-partition = &boot_partition;
/* We need to point where we want to place MCUboot RAM region. */
zephyr,sram = &cpuapp_sram_mcuboot_ram_region;
/* We need to point where we want to place the retained memory region that
* is shared with the application image and contains the image metadata.
*/
zephyr,bootloader-info = &boot_info0;
};
};
10 changes: 10 additions & 0 deletions ...rf_desktop/configuration/nrf54lm20dk_nrf54lm20a_cpuapp/images/mcuboot/app_release.overlay
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,10 @@
/*
* Copyright (c) 2025 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
*/

/* Application does not use cpuflpr core. Assign whole RRAM to cpuapp. */
&cpuapp_rram {
reg = < 0x0 DT_SIZE_K(2036) >;
};
20 changes: 20 additions & 0 deletions ...p/configuration/nrf54lm20dk_nrf54lm20a_cpuapp/images/mcuboot/app_release_ram_load.overlay
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,20 @@
/*
* Copyright (c) 2025 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
*/

#include "../../memory_map_ram_load.dtsi"

/ {
chosen {
/* We need to point where we want to place MCUboot code. */
zephyr,code-partition = &boot_partition;
/* We need to point where we want to place MCUboot RAM region. */
zephyr,sram = &cpuapp_sram_mcuboot_ram_region;
/* We need to point where we want to place the retained memory region that
* is shared with the application image and contains the image metadata.
*/
zephyr,bootloader-info = &boot_info0;
};
};
3 changes: 3 additions & 0 deletions ...p/configuration/nrf54lm20dk_nrf54lm20a_cpuapp/images/mcuboot/mcuboot_private_ram_load.pem
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,3 @@
-----BEGIN PRIVATE KEY-----

Check failure on line 1 in applications/nrf_desktop/configuration/nrf54lm20dk_nrf54lm20a_cpuapp/images/mcuboot/mcuboot_private_ram_load.pem

View check run for this annotation

SonarQubeCloud / SonarCloud Code Analysis

Make sure this private key gets revoked, changed, and removed from the code. 


See more on https://sonarcloud.io/project/issues?id=nrfconnect_sdk-nrf&issues=AZrAuD0MSchGjxeKEyly&open=AZrAuD0MSchGjxeKEyly&pullRequest=25661
MC4CAQAwBQYDK2VwBCIEIJR/vA+f1mEYMtTmAlXil9LRHemJZFEVbQ1VbKocJoJ/
-----END PRIVATE KEY-----
53 changes: 53 additions & 0 deletions .../nrf_desktop/configuration/nrf54lm20dk_nrf54lm20a_cpuapp/images/mcuboot/prj_ram_load.conf
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,53 @@
#
# Copyright (c) 2025 Nordic Semiconductor ASA
#
# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
#
CONFIG_SIZE_OPTIMIZATIONS=y

CONFIG_HW_STACK_PROTECTION=y

CONFIG_MAIN_STACK_SIZE=10240

CONFIG_BOOT_BOOTSTRAP=n

CONFIG_BOOT_VERSION_CMP_USE_BUILD_NUMBER=y

CONFIG_FLASH=y

# Enable retained memory and retention to support the MCUboot RAM load mode.
CONFIG_RETAINED_MEM=y
CONFIG_RETENTION=y
CONFIG_RETAINED_MEM_ZEPHYR_RAM=y
CONFIG_BOOT_SHARE_DATA=y
CONFIG_BOOT_SHARE_DATA_BOOTINFO=y
CONFIG_BOOT_SHARE_BACKEND_RETENTION=y

# Reduce memory consumption
CONFIG_BOOT_BANNER=n
CONFIG_NCS_BOOT_BANNER=n
CONFIG_SYS_CLOCK_EXISTS=n
CONFIG_CLOCK_CONTROL=n
CONFIG_NRF_GRTC_TIMER=n
CONFIG_NRF_GRTC_START_SYSCOUNTER=n
CONFIG_SPI_NOR=n
CONFIG_GPIO=n
CONFIG_SERIAL=n
CONFIG_CONSOLE=n
CONFIG_UART_CONSOLE=n
CONFIG_PRINTK=n
CONFIG_USE_SEGGER_RTT=n
CONFIG_COMMON_LIBC_MALLOC=n
CONFIG_COMMON_LIBC_CALLOC=n
CONFIG_COMMON_LIBC_REALLOCARRAY=n

# Activate Link Time Optimization (LTO)
CONFIG_LTO=y
CONFIG_ISR_TABLES_LOCAL_DECLARATION=y

# Improve debugging experience by disabling reset on fatal error
CONFIG_RESET_ON_FATAL_ERROR=n

# Set according to the configuration of the cpuapp_sram_app_rxm_region DTS node.
CONFIG_BOOT_IMAGE_EXECUTABLE_RAM_START=0x20000800
CONFIG_BOOT_IMAGE_EXECUTABLE_RAM_SIZE=500736
52 changes: 52 additions & 0 deletions ...ktop/configuration/nrf54lm20dk_nrf54lm20a_cpuapp/images/mcuboot/prj_release_ram_load.conf
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,52 @@
#
# Copyright (c) 2025 Nordic Semiconductor ASA
#
# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
#
CONFIG_SIZE_OPTIMIZATIONS=y

CONFIG_HW_STACK_PROTECTION=y

CONFIG_MAIN_STACK_SIZE=10240

CONFIG_BOOT_BOOTSTRAP=n

CONFIG_BOOT_VERSION_CMP_USE_BUILD_NUMBER=y

CONFIG_FLASH=y

# Enable retained memory and retention to support the MCUboot RAM load mode.
CONFIG_RETAINED_MEM=y
CONFIG_RETENTION=y
CONFIG_RETAINED_MEM_ZEPHYR_RAM=y
CONFIG_BOOT_SHARE_DATA=y
CONFIG_BOOT_SHARE_DATA_BOOTINFO=y
CONFIG_BOOT_SHARE_BACKEND_RETENTION=y

CONFIG_RESET_ON_FATAL_ERROR=y

# Reduce memory consumption
CONFIG_BOOT_BANNER=n
CONFIG_NCS_BOOT_BANNER=n
CONFIG_SYS_CLOCK_EXISTS=n
CONFIG_CLOCK_CONTROL=n
CONFIG_NRF_GRTC_TIMER=n
CONFIG_NRF_GRTC_START_SYSCOUNTER=n
CONFIG_SPI_NOR=n
CONFIG_GPIO=n
CONFIG_SERIAL=n
CONFIG_CONSOLE=n
CONFIG_UART_CONSOLE=n
CONFIG_PRINTK=n
CONFIG_USE_SEGGER_RTT=n
CONFIG_COMMON_LIBC_MALLOC=n
CONFIG_COMMON_LIBC_CALLOC=n
CONFIG_COMMON_LIBC_REALLOCARRAY=n

# Activate Link Time Optimization (LTO)
CONFIG_LTO=y
CONFIG_ISR_TABLES_LOCAL_DECLARATION=y

# Set according to the configuration of the cpuapp_sram_app_rxm_region DTS node.
CONFIG_BOOT_IMAGE_EXECUTABLE_RAM_START=0x20000800
CONFIG_BOOT_IMAGE_EXECUTABLE_RAM_SIZE=500736
Loading