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Original file line number Diff line number Diff line change
@@ -1,3 +1,3 @@
/*
* Copyright (c) 2026 Nordic Semiconductor ASA
*
Expand All @@ -7,9 +7,5 @@
#include "nrf9251dk_nrf9251_cpuapp.overlay"

&uart130 {
/delete-property/ memory-regions;
};

&uart120 {
/delete-property/ memory-regions;
/delete-property/memory-regions;

Check failure on line 10 in tests/zephyr/drivers/uart/uart_async_api/boards/nrf9251dk_nrf9251_cpuppr.overlay

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GitHub Actions / Run compliance checks on patch series (PR)

tests/zephyr/drivers/uart/uart_async_api/boards/nrf9251dk_nrf9251_cpuppr.overlay:10 Insert Space(s). Expecting 1. See https://docs.zephyrproject.org/latest/contribute/style/devicetree.html for more details.
};
Original file line number Diff line number Diff line change
Expand Up @@ -16,19 +16,19 @@
&pinctrl {
uart131_default_alt: uart131_default_alt {
group1 {
psels = <NRF_PSEL(UART_TX, 2, 3)>,
<NRF_PSEL(UART_RX, 2, 9)>,
<NRF_PSEL(UART_RTS, 1, 8)>,
<NRF_PSEL(UART_CTS, 1, 9)>;
psels = <NRF_PSEL(UART_RTS, 1, 4)>,
<NRF_PSEL(UART_CTS, 1, 11)>,
<NRF_PSEL(UART_RX, 2, 3)>,
<NRF_PSEL(UART_TX, 2, 9)>;
};
};

uart131_sleep_alt: uart131_sleep_alt {
group1 {
psels = <NRF_PSEL(UART_TX, 2, 3)>,
<NRF_PSEL(UART_RX, 2, 9)>,
<NRF_PSEL(UART_RTS, 1, 8)>,
<NRF_PSEL(UART_CTS, 1, 9)>;
psels = <NRF_PSEL(UART_RTS, 1, 4)>,
<NRF_PSEL(UART_CTS, 1, 11)>,
<NRF_PSEL(UART_RX, 2, 3)>,
<NRF_PSEL(UART_TX, 2, 9)>;
low-power-enable;
};
};
Expand Down
2 changes: 1 addition & 1 deletion west.yml
Original file line number Diff line number Diff line change
Expand Up @@ -65,7 +65,7 @@ manifest:
# https://developer.nordicsemi.com/nRF_Connect_SDK/doc/latest/zephyr/guides/modules.html
- name: zephyr
repo-path: sdk-zephyr
revision: 61983a74a0ae8529e77a0f4abb5b8646bc065555
revision: pull/4071/head
import:
# In addition to the zephyr repository itself, NCS also
# imports the contents of zephyr/west.yml at the above
Expand Down
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