softperipheral: Add initial sQSPI

.checkpatch.conf

@@ -31,3 +31,4 @@
 --exclude gzll
 --exclude nfc
 --exclude nrf_modem/include
+--exclude softperipheral

CODEOWNERS

@@ -47,3 +47,4 @@ doc/*                                     @b-gent
 /lc3/                                     @koffes @alexsven
 /nrf_fuel_gauge/                          @nordic-auko
 /nrf_wifi/                                @udaynordic @rajb9 @srkanordic
+/softperipheral/                          @lopeztel

README.rst

@@ -25,3 +25,4 @@ Refer to their respective documentation for more information.
    openthread/README
    nrf_rpc/README
    softdevice_controller/README
+   softperipheral/README

doc/links.txt

@@ -7,6 +7,8 @@
 
 .. _`nrfx`: https://github.com/NordicSemiconductor/nrfx/
 
+.. _`sdk-nrfxlib`: https://github.com/nrfconnect/sdk-nrfxlib
+
 .. _`TinyCBOR`: https://github.com/zephyrproject-rtos/tinycbor
 
 .. _`zcbor`: https://github.com/NordicSemiconductor/zcbor

softperipheral/README.rst

@@ -0,0 +1,11 @@
+.. _soft_peripherals:
+
+Soft peripherals
+################
+
+.. contents::
+   :local:
+   :depth: 2
+
+This documentation outlines the concept of soft peripherals, designed to emulate hardware peripherals using the Fast Lightweight Peripheral Processor (FLPR).
+It covers setup, integration, and operational guidelines for using each soft peripheral through the nrfx driver API, alongside detailed descriptions of limitations and performance considerations.

softperipheral/include/softperipheral_meta.h

@@ -0,0 +1,129 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+#ifndef SOFTPERIPHERAL_META_H__
+#define SOFTPERIPHERAL_META_H__
+
+#include <stdint.h>
+
+#define SOFTPERIPHERAL_META_HEADER_VERSION          (1)
+
+#define SOFTPERIPHERAL_META_SOFTPERIPHERAL_ID_SQSPI 0x45b1
+
+#if (SOFTPERIPHERAL_META_HEADER_VERSION == 1)
+
+#define SOFTPERIPHERAL_META_COMM_ID_REGIF       (1)
+#define SOFTPERIPHERAL_META_COMM_ID_JOBLIST     (2)
+
+#define SOFTPERIPHERAL_META_PLATFORM_DEVICE_15  (15)
+#define SOFTPERIPHERAL_META_PLATFORM_DEVICE_20  (20)
+
+#define SOFTPERIPHERAL_META_PLATFORM_PLATFORM_L (0)
+#define SOFTPERIPHERAL_META_PLATFORM_PLATFORM_H (1)
+
+#define SOFTPERIPHERAL_META_PLATFORM_SERIES_54  (54)
+
+#ifndef SOFTPERIPHERAL_META_SELF_BOOTING
+#define SOFTPERIPHERAL_META_SELF_BOOTING (0)
+#endif
+
+typedef struct
+{
+    union
+    {
+        struct
+        {
+            uint32_t magic          : 16;
+            uint32_t header_version : 4;
+            uint32_t comm_id        : 8;
+            uint32_t reserved0      : 3;
+            uint32_t self_boot      : 1; // If True, set INITPC to NVM address.
+                                         // If False, copy fw_code_size bytes from NVM to fw_ram_base_addr
+        };
+
+        uint32_t w0_raw;
+    };
+
+    union
+    {
+        struct
+        {
+            uint16_t softperiph_id;
+
+            union
+            {
+                struct
+                {
+                    uint16_t device   : 7;
+                    uint16_t platform : 2;
+                    uint16_t series   : 7;
+                };
+
+                uint16_t raw;
+            }        platform;
+        };
+
+        uint32_t w1_raw;
+    };
+
+    union
+    {
+        struct
+        {
+            uint32_t patch : 16;
+            uint32_t minor : 8;
+            uint32_t major : 8;
+        }        version;
+
+        uint32_t w2_raw;
+    };
+
+    union
+    {
+        struct
+        {
+            uint16_t fw_code_size;      // size / 16
+            uint16_t
+                     fw_ram_total_size; // size / 16. Must also include code (RAM CODE region), code RAM (.data/.bss/.stack/.heap), shared and/or allocatable RAM from the FW.
+        };
+
+        uint32_t w3_raw;
+    };
+
+    union
+    {
+        uint32_t fw_code_addr; // Address of where the code is compiled to run from.
+        uint32_t w4_raw;
+    };
+
+    union
+    {
+        uint32_t
+                 fw_ram_base_addr; // Dest address for code in case self_boot = False. Also, the RAM start address set by the FW in case of any RAM it needs.
+        uint32_t w5_raw;
+    };
+
+    union
+    {
+        struct
+        {
+            uint16_t fw_shared_ram_size; // size / 16
+            uint16_t fw_shared_ram_addr_offset;
+        };
+
+        uint32_t w6_raw;
+    };
+
+    union
+    {
+        uint32_t fw_vpr_save_ctx_addr;
+        uint32_t w7_raw;
+    };
+} softperipheral_metadata_t;
+
+#endif // (SOFTPERIPHERAL_META_HEADER_VERSION == 1)
+
+#endif // SOFTPERIPHEREAL_META_H__

softperipheral/include/softperipheral_regif.h

@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+#ifndef SOFTPERIPHERAL_REGIF_H__
+#define SOFTPERIPHERAL_REGIF_H__
+
+/* Shared between Host and Service, varies between platforms. */
+#if defined(NRF54L15_XXAA)
+#define SP_VPR_EVENT_IDX                  20
+#define NRF_VPR                           NRF_VPR00
+#define SP_VPR_TASK_DPPI_0_IDX            16 // Channel 0
+#define SP_VPR_TASK_CONFIG_IDX            18
+#define SP_VPR_TASK_ACTION_IDX            19
+#define SP_VPR_TASK_STOP_IDX              21
+#define SP_VPR_TASK_PROTOCOL_SPECIFIC_IDX 22
+#define SP_VPR_IRQHandler                 VPR00_IRQHandler
+#define SP_VPR_IRQn                       VPR00_IRQn
+#define SP_VPR_BASE_FREQ_HZ               128000000
+#elif defined(NRF54H20_XXAA)
+#define SP_VPR_EVENT_IDX                  28
+#define NRF_VPR                           NRF_VPR121
+#define SP_VPR_TASK_DPPI_0_IDX            24 // Channel 0
+#define SP_VPR_TASK_CONFIG_IDX            16
+#define SP_VPR_TASK_ACTION_IDX            17
+#define SP_VPR_TASK_STOP_IDX              22
+#define SP_VPR_TASK_PROTOCOL_SPECIFIC_IDX 23
+#define SP_VPR_IRQHandler                 VPR121_IRQHandler
+#define SP_VPR_IRQn                       VPR121_IRQn
+#define SP_VPR_BASE_FREQ_HZ               320000000
+#else
+#pragma warning "Processor not defined."
+#endif
+
+#if defined(NRF_APPLICATION)
+
+#ifndef SP_VPR_FIRMWARE_ADDRESS
+#define SP_VPR_FIRMWARE_ADDRESS 0x00040000
+#endif
+
+/* Config Synchronization Barrier (ASB). */
+#if 1
+#define __XSBx(R, P, T)                                                                    \
+    do {                                                                                   \
+        nrf_qspi2_core_dr_x(R, m_task_count, 20);                                          \
+        nrf_vpr_task_trigger(P, (nrf_vpr_task_t)offsetof(NRF_VPR_Type, TASKS_TRIGGER[T])); \
+        while (m_task_count != nrf_qspi2_core_dr_x_get(R, 21)) {                           \
+           __NOP();                                                                        \
+           __NOP();                                                                        \
+           __NOP();                                                                        \
+        }                                                                                  \
+        m_task_count++;                                                                    \
+    } while (0);
+#else
+#define __XSBx(R, P, T)                                                                    \
+    do {                                                                                   \
+        nrf_vpr_task_trigger(P, (nrf_vpr_task_t)offsetof(NRF_VPR_Type, TASKS_TRIGGER[T])); \
+    } while (0);
+#endif
+
+#define __CSB(R) __XSBx(R, NRF_VPR, SP_VPR_TASK_CONFIG_IDX);
+#define __ASB(R) __XSBx(R, NRF_VPR, SP_VPR_TASK_ACTION_IDX);
+#define __SSB(R) __XSBx(R, NRF_VPR, SP_VPR_TASK_STOP_IDX);
+#define __PSB(R) __XSBx(R, NRF_VPR, SP_VPR_TASK_PROTOCOL_SPECIFIC_IDX);
+#endif
+
+#endif // SOFTPERIPHERAL_REGIF_H__