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[nrf fromtree] Fixes in GPPI for nrf9251 #4043

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Merged
rlubos merged 4 commits into from
May 18, 2026
Merged

[nrf fromtree] Fixes in GPPI for nrf9251 #4043

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c3956d6
[nrf fromtree] dts: vendor: nordic: nrf54h20: Add missing property fo…
nordic-krch May 5, 2026
036ed0e
[nrf fromtree] soc: nordic: common: Fix SD2PPI global configuration
nordic-krch May 6, 2026
d0f2945
[nrf fromtree] soc: nordic: common: gppi_sd2ppi: Fix NRF_SPU dependency
nordic-krch May 6, 2026
1c0a084
[nrf fromtree] modules: hal_nordic: nrfx: Enable external PPIB function
nordic-krch May 6, 2026
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1 change: 1 addition & 0 deletions dts/vendor/nordic/nrf54h20.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -885,6 +885,7 @@
reg = <0x8ef000 0x1000>;
status = "disabled";
channels = <8>;
offset = <16>;
};

cpuppr_vpr: vpr@908000 {
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4 changes: 4 additions & 0 deletions modules/hal_nordic/nrfx/nrfx_kconfig.h
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Expand Up @@ -438,6 +438,10 @@
#define NRFX_WDT_CONFIG_LOG_ENABLED 1
#endif

#ifdef CONFIG_NRFX_GPPI_SD2PPI_GLOBAL
#define NRFX_GPPI_CONFIG_DPPI_PPIB_EXT_FUNC 1
#endif

#ifdef CONFIG_NRF52_ANOMALY_109_WORKAROUND
#define NRF52_ERRATA_109_ENABLE_WORKAROUND 1
#define NRFX_PWM_NRF52_ANOMALY_109_EGU_INSTANCE \
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7 changes: 4 additions & 3 deletions soc/nordic/common/gppi_init.c
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Expand Up @@ -143,11 +143,12 @@

#if defined(CONFIG_NRFX_GPPI) && !defined(CONFIG_NRFX_GPPI_V1)

/* For nrf54h20 GPPI requires that ironside communication is up so delay the initialization. */
#define GPPI_INIT_STATE COND_CODE_1(IS_ENABLED(CONFIG_SOC_NRF54H20_CPUAPP), (POST_KERNEL), (EARLY))
/* For SD2PPI GPPI it is required that ironside communication is up so delay the initialization. */
#define GPPI_INIT_STATE \
COND_CODE_1(IS_ENABLED(CONFIG_NRFX_GPPI_SD2PPI_GLOBAL), (POST_KERNEL), (EARLY))

#define GPPI_INIT_PRIO \
COND_CODE_1(IS_ENABLED(CONFIG_SOC_NRF54H20_CPUAPP), \
COND_CODE_1(IS_ENABLED(CONFIG_NRFX_GPPI_SD2PPI_GLOBAL), \

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soc/nordic/common/gppi_init.c:151 
-#define GPPI_INIT_STATE                                                         \
+#define GPPI_INIT_STATE                                                                            \
 	COND_CODE_1(IS_ENABLED(CONFIG_NRFX_GPPI_SD2PPI_GLOBAL), (POST_KERNEL), (EARLY))
 
-#define GPPI_INIT_PRIO                                                          \
+#define GPPI_INIT_PRIO                                                                             \

See https://docs.zephyrproject.org/latest/contribute/guidelines.html#clang-format for more details.
(UTIL_INC(CONFIG_IRONSIDE_SE_CALL_INIT_PRIORITY)), (0))

SYS_INIT(gppi_init, GPPI_INIT_STATE, GPPI_INIT_PRIO);
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4 changes: 2 additions & 2 deletions soc/nordic/common/nrfx_gppi_sd2ppi_global.c
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Expand Up @@ -420,11 +420,11 @@
NRF_SPU133,
NRF_SPU134,
NRF_SPU135,
IF_ENABLED(NRFX_INSTANCE_PRESENT(SPU136), (NRF_SPU136,))
IF_ENABLED(NRFX_INSTANCE_PRESENT(SPU137), (NRF_SPU137,))
IF_ENABLED(DT_NODE_EXISTS(DT_NODELABEL(dppic135)), (NRF_SPU136,))
IF_ENABLED(DT_NODE_EXISTS(DT_NODELABEL(dppic136)), (NRF_SPU137,))
NRF_SPU122,
};
uint32_t out_mask = 0;

Check notice on line 427 in soc/nordic/common/nrfx_gppi_sd2ppi_global.c

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soc/nordic/common/nrfx_gppi_sd2ppi_global.c:427 
-	static const NRF_SPU_Type * spu_addr[] = {
+	static const NRF_SPU_Type *spu_addr[] = {
 		NRF_SPU131,
 		NRF_SPU132,
 		NRF_SPU133,
 		NRF_SPU134,
 		NRF_SPU135,
-		IF_ENABLED(DT_NODE_EXISTS(DT_NODELABEL(dppic135)), (NRF_SPU136,))
-		IF_ENABLED(DT_NODE_EXISTS(DT_NODELABEL(dppic136)), (NRF_SPU137,))
-		NRF_SPU122,
-	};
+		IF_ENABLED(DT_NODE_EXISTS(DT_NODELABEL(dppic135)), (NRF_SPU136,)) IF_ENABLED(DT_NODE_EXISTS(DT_NODELABEL(dppic136)), (NRF_SPU137,)) NRF_SPU122,
+			};

See https://docs.zephyrproject.org/latest/contribute/guidelines.html#clang-format for more details.
uint32_t in_mask = *ch_mask;
struct periphconf_entry entries[IRONSIDE_SE_PERIPHCONF_INLINE_READ_MAX_COUNT];
uint8_t entries_idx[IRONSIDE_SE_PERIPHCONF_INLINE_READ_MAX_COUNT];
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