ARM: imx: init ENET RGMII tx clock source

Set GPR5[9] on imx6dp/qp to select clock from internal PLL_enet.

Signed-off-by: Rustam Abdullaev <rustamabd@gmail.com>

Author: rustyx

arch/arm/mach-imx/mach-imx6q.c

@@ -119,11 +119,18 @@ static void __init imx6q_1588_init(void)
 				IMX6Q_GPR1_ENET_CLK_SEL_ANATOP :
 				IMX6Q_GPR1_ENET_CLK_SEL_PAD;
 	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
-	if (!IS_ERR(gpr))
+	if (!IS_ERR(gpr)) {
 		regmap_update_bits(gpr, IOMUXC_GPR1,
 				IMX6Q_GPR1_ENET_CLK_SEL_MASK,
 				clksel);
-	else
+		if (clksel == IMX6Q_GPR1_ENET_CLK_SEL_ANATOP &&
+		    cpu_is_imx6q() &&
+		    imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) {
+			regmap_update_bits(gpr, IOMUXC_GPR5,
+					IMX6Q_GPR5_ENET_TX_CLK_SEL,
+					IMX6Q_GPR5_ENET_TX_CLK_SEL);
+		}
+	} else
 		pr_err("failed to find fsl,imx6q-iomuxc-gpr regmap\n");
 
 	clk_put(enet_ref);

include/linux/mfd/syscon/imx6q-iomuxc-gpr.h

@@ -240,6 +240,7 @@
 #define IMX6Q_GPR4_IPU_RD_CACHE_CTL		BIT(0)
 
 #define IMX6Q_GPR5_L2_CLK_STOP			BIT(8)
+#define IMX6Q_GPR5_ENET_TX_CLK_SEL		BIT(9)
 #define IMX6Q_GPR5_SATA_SW_PD			BIT(10)
 #define IMX6Q_GPR5_SATA_SW_RST			BIT(11)
 #define IMX6Q_GPR5_PRE_PRG_SEL0_MASK		(0x3 << 12)