Tlv conversion serv bufreg#165
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Correct a typo in `fusesoc library add fusesoc_cores https://github.com/fusesoc/fusesoc_cores` to `fusesoc library add fusesoc_cores https://github.com/fusesoc/fusesoc-cores`
Instead of shifting shamt all the way to bits 4:0, we just shift 8 steps. This saves some energy and allows us to be finished before cnt_done.
This allows removing the stage_two_req register as well.
Added clarity and consistency w/some basic formatting changes and revisions to the "Getting started" section.
- Fix 'addded' typo to 'added' - Correct 'just enough runs' to 'just enough to run' - Remove redundant 'added included into' to 'included in' - Fix duplicate 'extension' in 'M-extension extension' - Add missing article 'the' before 'latest version'
Useful for CC="clang --target=..." so you don't need a full GCC toolchain. Signed-off-by: Alfred Persson Forsberg <cat@catcream.org>
Follow the 6 steps to add support for a new target.
Step 1: Locate input and output pins.
Step 2: Add pin constraint file. This covers clock input, LED and UART
output.
Step 3: Create a clock generator. The chip has no internal clock
generator so the external 12 MHz clock is used.
Step 4: Add top level servant_ice40_cm36 which connects the one-wire
output of servant to the LED pin.
Step 5: Add fileset including the new top level and pin constraints.
Step 6: Add target icesugar-nano.
Establish the conversion environment and regression flow for converting rtl/serv_bufreg.v to TL-Verilog, with the module in its initial verbatim \SV-copy state (not yet refactored). - tlv/serv_bufreg.tlv: initial copy of the Verilog in an \SV block. - tlv/verilog/serv_bufreg.v + _gen.v: SandPiper output; rtl/serv_bufreg.v and rtl/serv_bufreg_gen.v symlink into it. The SandPiper //_\ header is stripped to keep line numbers aligned with data/verilator_waiver.vlt, which waives serv_bufreg unused signals by line number. - serv.core: list serv_bufreg_gen.v just before serv_bufreg.v so the `BOGUS_USE macro definition is in scope (shared across files in order). - tlv/env/Dockerfile.project + docker-compose.yml: add FuseSoC (SERV's test tool) on top of the base image. - tlv/regress/regress.sh: regress via SERV's own FuseSoC targets (lint W=1, lint W=4, hello_uart servant sim). All pass. - tlv/project_instructions/project_specific_instructions.md: conversion guidance (preparation, params, clock-enable note, regression). - tlv/.gitignore: exclude regress/work/ and env/.env. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Incrementally refactor serv_bufreg.tlv from a verbatim \SV copy into
TL-Verilog, one FEV-verified step at a time:
- clr_lsb and the {c,q} carry/sum adder -> TLV ($clr_lsb, $carry_and_sum,
$c, $q), bridging q back to \SV for the generate blocks.
- c_r carry register -> TLV (>>1 flop), with a `wire clk = i_clk;` bridge
since SandPiper-inferred flops clock off `clk`.
- o_dbus_adr and o_ext_rs1 -> TLV (*o_port = expr).
The W-parameterized data shift-register datapath stays in \SV `generate`:
the W==1 and W==4 branches are structurally different and write the same
register, and TL-Verilog has no `generate` (M5 macros can't branch on a
Verilog elaboration parameter), so a TLV $data would double-drive `data`
when W==4 is elaborated. See tlv/tracker.md.
Tooling:
- tlv/regress/fev.sh: regenerate from .tlv, then Yosys sequential
equivalence vs serv_bufreg_golden.v for W=1 and W=4
(techmap; equiv_struct; equiv_simple; equiv_induct). Validated to catch
a real injected bug.
- serv.core: mark serv_bufreg_gen.v is_include_file (SandPiper now
`include's it once there is TLV content).
- tlv/tracker.md: conversion log, SandPiper mechanics, issues/patterns.
FEV (W=1, W=4) and regress.sh (lint W=1/W=4, hello_uart sim) both pass.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Convert the remaining gen_w_eq_1 / gen_lsb_w_4 generate blocks using a ternary approach: compute both the W=1 and W=4 datapath values as unconditional TLV signals and select with (W == 1) ? ... : ..., letting synthesis constant-fold the dead path. The \SV section now contains only the module header and the clk bridge. Add two equiv_add -try calls to fev.sh for the c_r carry register, which equiv_make's find_same_wires misses (it only reaches outputs through another register stage). FEV passes for both W=1 and W=4. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
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This PR converts the width-independent portions of
serv_bufreg.vto TL-Verilog using the desktop-agent conversion flow. The work includes SERV-specific setup, incremental FEV verification (fev.sh), regression testing with existing FuseSoC targets, and documentation of issues and findings intracker.md. The converted logic includeso_dbus_adr,o_ext_rs1, carry-generation logic, and thec_rregister, with FEV, lint, and simulation passing throughout the conversion process. The W-parameterized datapath remains in\SVbecause theW==1andW==4elaborations are structurally different and would require additional design decisions before a safe TL-Verilog conversion.