Display name: RISCV32IMAC Processor Core
UID: ip-000020
Family: riscv-core
Category: processor
Repository: git@github.com:openecos-projects/riscv32imac-core.git
Upstream: internal development item from ref/正在开发的IP.docx
Current baseline: planning document snapshot from 2026-06-15
License: proprietary or undetermined
Status: planned, in verification before tapeout validation
This repository is managed as a child repository of ip-catalog.
RISC-V RV32IMAC processor core with instruction and data caches, multi-stage pipeline, AXI memory interface, RISC-V Debug support, and CoreMark/MHz above 2.
The local repository currently contains metadata only. RTL, ISA compliance results, CoreMark logs, debug validation, and tapeout verification evidence should be added when available.
docs/ Datasheet and provenance notes
reports/ Review, lint, simulation, or synthesis report summaries
data/ip/processor/ip-000020.yaml
Local metadata source:
ip.yaml