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feat(rdna2): default gfx1030 MoE accumulation to fp32 - #152
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VLLM_RDNA2_MOE_FP32_ACCUM now defaults on. Set it to 0 for the packed fp16 CAS-64 epilogue. Comments no longer claim gfx1030 emits v_global_atomic_add_f32; atomicAdd(float*) is a CAS-32 retry loop there. Co-authored-by: BlivionIaG <BlivionIaG@users.noreply.github.com>
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Closing: this re-proposes the fp32 MoE-epilogue default, which was tried on 2026-09-30 and reverted to CAS on 2026-10-01. Recorded decision ( |
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Overview
VLLM_RDNA2_MOE_FP32_ACCUMnow defaults on for the gfx1030 fused MoE epilogue (fp32 scratch, one fp32→fp16 cast).=0keeps the packed-fp16 CAS-64 path. Comments that called the fp32 path nativev_global_atomic_add_f32were wrong on gfx1030: that opcode is gfx11+, andatomicAdd(float*)lowers to CAS-32 retry loops.No open
opengfx1030/vllm-rdnaPR changes this default (57 open PRs scanned for fp32 / accum / epilogue). The env var does not appear on openvllm-project/vllmPRs. This PR targetsrdna_extrasonly.AI assistance was used (Cursor Agent).
Claims
1, andtrueselect fp32 accumulation formoe_gptq_gemm_rdna2(W4A16) andmoe_w4a8_gemm_rdna2(W4A8).VLLM_RDNA2_MOE_FP32_ACCUM=0(alsofalse) before vLLM is imported. A per-callfp32_accum=Falsestill overrides one call.How to opt out
export VLLM_RDNA2_MOE_FP32_ACCUM=0Recipes and
tools/rdna/serve_rdna.shdo not set this variable, so the registry default is what serving uses. The production call sites omitfp32_accumand follow the env. The torch op schema default was alreadyfp32_accum=True; the wrapper was the piece that still passed false.Changed files
vllm/envs.py— annotation defaultTrue; getenv fallback"1".vllm/_custom_ops.py— comment only. Still reads the env once at import.csrc/rocm/moe_accum_rdna2.cuh— comments only.csrc/rocm/moe_q_gemm_rdna2.cu— comments only.csrc/rocm/moe_w4a8_rdna2.cu— comments only.docs/rdna2/moe-epilogue-accum.md— default, opt-out, ISA, historical matrix labeled as historical.docs/rdna2/tuning.md— env table default1.tests/test_envs.py— CPU test of unset /1/truevs0/false.tests/kernels/quantization/test_rdna2_moe_w4a16.py— docstrings. The old "default off" test now says it forces the flag off.docs/rdna/serving.mdand the README do not mention this variable. Serving already points kernel defaults atdocs/rdna2/tuning.md.Validation
CPU parser, from a temp venv (CPU torch only so
import vllmworks;--noconftestbecausetests/conftest.pyneeds the full test extra). Fork pinstorch==2.12.0+rocm7.14.0and ROCm 7.14.0 are unchanged.Result: 1 passed.
ISA check, host clang 18.1.3 (
-target amdgcn-amd-amdhsa -mcpu=gfx1030 -O3 -nogpulib), not the ROCm 7.14 hipcc. No ROCm device library here, so vLLM was not rebuilt. Anatomicrmw faddof four floats (themoe_accum_row<float>shape, with!amdgpu.no.fine.grained.memory) emits fourglobal_atomic_cmpswaploops at offsets 0/4/8/12 pluss_cbranch_execnz. Noglobal_atomic_add_f32. The source callsatomicAdd(out + j, vals[j])four times. The packed-fp16 path is the existingatomicCASonunsigned long longinatomic_add_pk4_f16(one CAS-64). The gfx1030 ISA has nov_global_atomic_add_f32(gfx11+), so the ROCm pin cannot emit it either. Same conclusion as rdna-hip-wiki#45.No gfx1030 GPU in this environment.
tests/kernels/quantization/test_rdna2_moe_w4a16.pywas not run. Those tests are@gfx1030_onlyand still monkeypatch both modes.W4A16
q_gemm_rdna2*/ fdot2, EXL3exl3_dot2_*,w4a8_sdot4, andrdna_allreduceare untouched. No stub signature or arch-guard edit, so the gfx1030;gfx1100 split indocs/rdna2/build-break-2026-10-31.mdis unchanged. That dual-arch build was not recompiled here.V620 validation still required
Do not treat the new default as validated until a V620 MoE decode run under contention (small batch, top-k > 1, many experts writing the same output rows) reports both of the following against the fp16 opt-out (
VLLM_RDNA2_MOE_FP32_ACCUM=0):The fp32 path is four CAS-32 retry loops per row; the current packed-fp16 path is one CAS-64. The CAS-32 loops may be slower. This PR claims no tok/s number. The 2026-09-30 matrix kept in
docs/rdna2/moe-epilogue-accum.mdis historical context only.Details
The registry default was
"False"while several kernel comments already called fp32 the default and described it as a native atomic with no CAS. Serving goes through_custom_ops, which resolvesfp32_accum=Nonefrom that env at import, so the shipped path was packed-fp16 CAS-64.The fp32 scratch, the cast kernel, and
atomicAddwere already in tree. This change flips the default and corrects the comments. The env is a torch.compile factor, so an unset worker's compile-cache key changes with the resolved flag.Design fit: no scheduler or model-runner change, no new kernel, opt-out preserved. Tradeoff: one fp16 rounding at the cast, against a possible decode slowdown under contention that still needs a V620 measurement.
Pull Request Checklist
I used vLLM's
/pr-checklistskill. (Mandatory for agents, optional for humans).AI assistance was used during the creation of this PR.
Design Fit: Minimizes impact on core components, reuses existing functionality, and justifies added complexity.
Testing and Validation: Validates the change and ensures any added tests are meaningful and reliable, with CI coverage or documented CI resource constraints and validation performed outside CI.
Code Quality and Style: Keeps code and comments clear and concise, and updates relevant documentation and examples.
Pull Request Contents: Includes a brief summary and relevant links, supports claims with evidence, explains root causes and implementation trade-offs, and follows the contributing guide.
BEFORE SUBMITTING, PLEASE READ https://docs.vllm.ai/en/latest/contributing