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feat(qwen4-prep): Qwen4 config probe, monokernel stage planner, opt-in dense MLP + 4 upstream Qwen4Exp backports - #164
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BlivionIaG wants to merge 8 commits into
Draft
BlivionIaG wants to merge 8 commits into
BlivionIaG wants to merge 8 commits into
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Signed-off-by: BlivionIaG <kev29lt@gmail.com>
Signed-off-by: BlivionIaG <kev29lt@gmail.com>
Signed-off-by: BlivionIaG <kev29lt@gmail.com>
…n int64 (vllm-project#64820) Signed-off-by: Sean Bell <seanbell@resolve.ai> Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg> Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com> Co-authored-by: Thien Tran <gau.nernst@yahoo.com.sg> Co-authored-by: Kimi Code <noreply@moonshot.cn> Co-authored-by: vllm-agent <claw@inferact.ai>
…y profiling (vllm-project#60490) Signed-off-by: Nick Kuhn <95254386+nkuhn-vmw@users.noreply.github.com> Co-authored-by: Claude Opus 5.5 (1M context) <noreply@anthropic.com> Co-authored-by: Thien Tran <gau.nernst@yahoo.com.sg>
…/k/v and a BF16 QSA indexer (vllm-project#62318) Signed-off-by: Seungryong Kim <137975233+srkim-business@users.noreply.github.com> Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg> Co-authored-by: Thien Tran <gau.nernst@yahoo.com.sg> Co-authored-by: Kimi <noreply@moonshot.ai>
Signed-off-by: Stefano Castagnetta <scastagnetta@nvidia.com> Signed-off-by: Trosfy <61226342+Trosfy@users.noreply.github.com> Co-authored-by: Kartikey Vyas <kartikey@artificialanalysis.ai> Co-authored-by: Trosfy <61226342+Trosfy@users.noreply.github.com> Co-authored-by: Artem Perevedentsev <aperevedents@nvidia.com>
Signed-off-by: BlivionIaG <kev29lt@gmail.com>
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Draft: GPU validation pending. Merges cleanly into
rdna_extras(branch is 189 commits behind).Fork commits:
f53fd9e74dopt-in config probe for Qwen4-family checkpoints (vllm/models/qwen4_prep/config_probe.py)142c93cae4config-to-stage-graph planner for the Qwen4 monokernel (qwen4_prep/mono_plan.py)962054a6f5opt-in dense MLP for Qwen4 checkpoints without experts (common/dense_mlp.py,mlp_selection.py)c3971d2c89test fix (TP group init for the dense MLP meta tests)Upstream backports (applied in order without conflicts):
22196687e9[Kernel] Qwen4Exp: compute HyperConnection and PLE gate row offsets in int64 vllm-project/vllm#64820 int64 HyperConnection / PLE gate row offsets (amd/ops/hc.py,nvidia/ops/hc.py)d92580ced1[Bugfix][Qwen4Exp] Reserve QSA indexer prefill workspace during memory profiling vllm-project/vllm#60490 reserve the QSA indexer prefill workspace during memory profilingb1938a5414[Bugfix][Model] Qwen3.8-Flash-Next: load checkpoints with quantized q/k/v and a BF16 QSA indexer vllm-project/vllm#62318 Flash-Next: load checkpoints with quantized q/k/v and a BF16 QSA indexer4c217d501b[Qwen4Exp] PLE disk offload vllm-project/vllm#59958 PLE disk offload (ple_offload_modeconfig surface)Touches the production Flash-Next path:
vllm/models/qwen4_exp/amd/model.pyandcommon/ngram_embedding.py.Checks so far:
py_compileon every touched file; the CPU tests intools/rdna/qwen4/(config probe, dense MLP, mono plan).Before ready:
vllm/v1/ple_offload/,VLLM_PLE_CPU_OFFLOAD,VLLM_PLE_QUANT_DIR). Readiness doc: keep the sidecar, take only the config surface, never run two offload mechanisms. Confirm the default path still goes through the sidecar.docs/rdna2/qwen4/readiness.md, table 'GPU validation: pending'): compiled F&P boot offlashnext-mtp2andflashnext-mtp0(PLE int4), greedy probes, PPL, prefix cache, 16k/1k c8 vsrdna_extras, 0 faults.rdna_extrasin first.