Instruction Tracing by MaxCThales · Pull Request #3071 · openhwgroup/cva6

MaxCThales · 2025-08-06T09:55:08Z

Integration of instr_tracing in corev_apu

More testing in real conditions pinpointed some bugs: * `iretire` value was sometimes off by 1 because `counter_o` was not cleared correctly in instr_to_trace * A dimension was redundant in the `itype` field of iti_to_encoder * `valid_o` in cva6_iti was not being cleared when the output was not valid * Reset value fix for enum itype and priv

* Added modularity to the ITI module to ensure compatibility with an instruction-by-instruction encoder configuration (`block_mode = 0`) * Moved the code to corev_apu/instr_tracing/ITI for better project structure * Modified the `iti_test.sh` to accept an executable as an argument * ITI is integrated into `ariane_xilinx.sv` and `ariane_testharness.sv`

* Add `dpti_ctrl.vhd` from Digilent in the `ariane_xilinx.sv` platform * Add in the fpga flow the tcl files to build `xlnx_dpti_clk` needed for the dpti_ctrl * Add `slicer_DPTI.sv` to convert encapsulated packet (320 bits) into slices (8 bits) * Add constraints in `ariane.xdc` and `genesy-2.xdc` to correctly synthesize with Vivado 2018.2 * Modify the Makefile to add dpti in the fpga build

* Adding script for debug and format conversion in /Decapsuler * Adding in /SW the Receiver_DPTI that catch slices, reconstruct encapsulated packet and decapsulate them * Adding json files in /SW/FPGA_auto to custom Vscode in order to automate remote debugging (with openocd, gdb)

* Add Documentation about Instruction Tracing, the work done, the choice made, the work that remains to be done * Upgrading the previous CI Test using the referenceFlow from the E-Trace Specification for greater robustness and modularity

github-actions · 2025-08-06T09:56:08Z

-    assign rvfi_csr_o.``CSR_NAME``.wdata = CSR_ENABLE_COND ? { {{CVA6Cfg.XLEN-$bits(CSR_SOURCE_NAME)}, CSR_SOURCE_NAME} } : 0; \
-    assign rvfi_csr_o.``CSR_NAME``.rmask = CSR_ENABLE_COND ? 1 : 0; \
-    assign rvfi_csr_o.``CSR_NAME``.wmask = (rvfi_csr_o.``CSR_NAME``.rdata != {{CVA6Cfg.XLEN - $bits(CSR_SOURCE_NAME)}, CSR_SOURCE_NAME}) && CSR_ENABLE_COND;
+  `define CONNECT_RVFI_FULL(CSR_ENABLE_COND, CSR_NAME, CSR_SOURCE_NAME) \


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

`define CONNECT_RVFI_FULL(CSR_ENABLE_COND, CSR_NAME, CSR_SOURCE_NAME) \

`define CONNECT_RVFI_FULL(CSR_ENABLE_COND, CSR_NAME,

CSR_SOURCE_NAME) \

github-actions · 2025-08-06T09:56:08Z


-  `CONNECT_RVFI_FULL(CVA6Cfg.RVS, sstatus,
-                     csr.mstatus_extended & SMODE_STATUS_READ_MASK[CVA6Cfg.XLEN-1:0])
+    `CONNECT_RVFI_FULL(CVA6Cfg.RVS, sstatus, csr.mstatus_extended & SMODE_STATUS_READ_MASK[CVA6Cfg.XLEN-1:0])


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

`CONNECT_RVFI_FULL(CVA6Cfg.RVS, sstatus, csr.mstatus_extended & SMODE_STATUS_READ_MASK[CVA6Cfg.XLEN-1:0])

`CONNECT_RVFI_FULL(CVA6Cfg.RVS, sstatus,

csr.mstatus_extended & SMODE_STATUS_READ_MASK[CVA6Cfg.XLEN-1:0])

github-actions · 2025-08-06T09:56:08Z

    for (i = 0; i < 16; i++) begin
-      `CONNECT_RVFI_FULL(1'b1, pmpaddr[i], {
-                         csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:1], pmpcfg_q[i].addr_mode[1]})
+      `CONNECT_RVFI_FULL(1'b1, pmpaddr[i], {csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:1], pmpcfg_q[i].addr_mode[1]})


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

`CONNECT_RVFI_FULL(1'b1, pmpaddr[i], {csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:1], pmpcfg_q[i].addr_mode[1]})

`CONNECT_RVFI_FULL(1'b1, pmpaddr[i], {

csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:1], pmpcfg_q[i].addr_mode[1]})

github-actions · 2025-08-06T10:39:58Z