Adding support for Qmtech Kintex-7 dev board.

config/derivlist.txt

@@ -65,6 +65,9 @@ EXT_MEM_RANGE       64'h0FFFFFFF
 deriv fpgagenesys2 fpga
 EXT_MEM_RANGE       64'h3FFFFFFF
 
+deriv fpgaqmtechk7 fpga
+EXT_MEM_RANGE       64'h0FFFFFFF
+
 deriv fpgavcu108 fpga
 EXT_MEM_RANGE       64'h7FFFFFFF
 

fpga/constraints/constraints-qmtechk7.xdc

@@ -0,0 +1,243 @@
+# The main clocks are all autogenerated by the Xilinx IP
+# mmcm_clkout0 is the clock output of the DDR3 memory interface / 4.
+# This clock is not used by wally or the AHB Bus. However it is used by the AXI BUS on the DD3 IP.
+
+create_generated_clock -name SPISDCClock -source [get_pins mmcm/clk_out3] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SPICLK]
+
+##### clock #####
+set_property LOC F22 [get_ports default_50mhz_clk]  
+set_property IOSTANDARD LVCMOS33 [get_ports default_50mhz_clk]
+
+# Clocks and Resets (adjust to match board)
+set_property IOSTANDARD LVCMOS33 [get_ports default_200mhz_clk]
+set_property IOSTANDARD LVCMOS33 [get_ports resetn]
+set_property IOSTANDARD LVCMOS33 [get_ports south_reset]
+
+# Clock constraints
+create_clock -period 20.000 -name clk_50m [get_ports default_50mhz_clk]
+create_clock -period 5.000 -name sys_clk [get_ports sys_clk_i]
+create_clock -period 5.000 -name idelay_refclk [get_ports clk_ref_i]
+#create_clock -period 5.000 -name mig_clk_200m [get_ports sys_clk_i]
+
+set_property CLOCK_BUFFER_TYPE BUFG [get_nets wallypipelinedsoc/clk_out3_mmcm]
+
+# *** don't love this hack.  RT: Don't understand why the recomemded input clock is causing a clock routing issue.  
+set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets default_50mhz_clk]
+
+##### RVVI Ethernet (not working yet) ####
+set_property IOSTANDARD LVCMOS33 [get_ports {phy_txd[*] phy_tx_en}]
+set_property PACKAGE_PIN C16 [get_ports {phy_txd[0]}];
+set_property PACKAGE_PIN U24 [get_ports {phy_txd[1]}];
+set_property PACKAGE_PIN A20 [get_ports {phy_txd[2]}];
+set_property PACKAGE_PIN B20 [get_ports {phy_txd[3]}];
+set_property PACKAGE_PIN F20 [get_ports {phy_tx_en}]
+
+
+##### GPI ####
+set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { GPI[0] }] ; # GPIO4 on JP3
+set_property -dict { PACKAGE_PIN D21 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { GPI[1] }] ; # GPIO5 on JP3
+set_property -dict { PACKAGE_PIN D10   IOSTANDARD LVCMOS33 } [get_ports { GPI[2] }]; # JP3 GPIO6
+set_property -dict { PACKAGE_PIN B12   IOSTANDARD LVCMOS33 } [get_ports { GPI[3] }]; # JP3 GPIO7
+set_input_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 0.000 [get_ports {GPI[*]}]
+set_input_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 0.000 [get_ports {GPI[*]}]
+set_max_delay -from [get_ports {GPI[*]}] 20.000
+
+
+##### GPO ####
+# User LEDs
+set_property -dict { PACKAGE_PIN R26 IOSTANDARD LVCMOS33 } [get_ports { GPO[0] }] ; # LED2
+set_property -dict { PACKAGE_PIN P26 IOSTANDARD LVCMOS33 } [get_ports { GPO[1] }] ; # LED3
+set_property -dict { PACKAGE_PIN N26 IOSTANDARD LVCMOS33 } [get_ports { GPO[2] }] ; # LED4
+# RPI connector pins
+set_property -dict { PACKAGE_PIN C12   IOSTANDARD LVCMOS33 } [get_ports { GPO[3] }]; 
+set_property -dict { PACKAGE_PIN B11   IOSTANDARD LVCMOS33 } [get_ports { GPO[4] }]; 
+set_max_delay -to [get_ports {GPO[*]}] 20.000
+set_output_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 0.000 [get_ports {GPO[*]}]
+set_output_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 0.000 [get_ports {GPO[*]}]
+
+
+
+##### UART #####
+# JP5 is on bank #14 (3.3V)
+set_property -dict { PACKAGE_PIN AE22   IOSTANDARD LVCMOS33 } [get_ports { UARTSout }]; #JP5, pin 7 (TX)
+set_property -dict { PACKAGE_PIN AF22   IOSTANDARD LVCMOS33 } [get_ports { UARTSin }]; #JP5, pin 8 (RX)
+set_input_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 0.000 [get_ports UARTSin]
+set_input_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 0.000 [get_ports UARTSin]
+set_output_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 0.000 [get_ports UARTSout]
+set_output_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 0.000 [get_ports UARTSout]
+
+
+##### reset #####
+#************** reset is inverted
+set_property -dict { PACKAGE_PIN V26   IOSTANDARD LVCMOS33 } [get_ports { south_reset }]; # SW2 on the board
+set_property -dict { PACKAGE_PIN U26   IOSTANDARD LVCMOS33 } [get_ports { resetn }]; # SW3 on the board
+
+set_input_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 2.000 [get_ports resetn]
+set_input_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 2.000 [get_ports resetn]
+set_max_delay -from [get_ports resetn] 20.000
+set_false_path -from [get_ports resetn]
+
+set_input_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 2.000 [get_ports south_reset]
+set_input_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 2.000 [get_ports south_reset]
+set_max_delay -from [get_ports south_reset] 20.000
+set_false_path -from [get_ports south_reset]
+
+
+
+##### SD Card I/O #####
+###########################################################################################
+# Digilent micro SD card PMOD (or equivalent) connected to J13
+###########################################################################################
+# pin selection
+set_property PACKAGE_PIN A24 [get_ports SDCCS]
+set_property PACKAGE_PIN B26 [get_ports SDCCmd]
+set_property PACKAGE_PIN D26 [get_ports SDCIn]
+set_property PACKAGE_PIN F25 [get_ports SDCCLK]
+set_property PACKAGE_PIN C26 [get_ports SDCCD]
+# NC
+set_property PACKAGE_PIN E26 [get_ports SDCWP] 
+set_property PULLTYPE PULLUP [get_ports {SDCCS SDCIn SDCCD SDCWP SDCCmd}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SDCCS SDCCmd SDCIn SDCCLK SDCCD SDCWP}]
+
+set_output_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCCS}]
+set_output_delay -clock [get_clocks SPISDCClock] -max -add_delay 10.000 [get_ports {SDCCS}]
+set_input_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCIn}]
+set_input_delay -clock [get_clocks SPISDCClock] -max -add_delay 10.000 [get_ports {SDCIn}]
+set_output_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.000 [get_ports {SDCCmd}]
+set_output_delay -clock [get_clocks SPISDCClock] -max -add_delay 6.000 [get_ports {SDCCmd}]
+
+
+### ddr3 ####
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[0]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[1]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[2]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[3]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[4]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[5]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[6]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[7]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[8]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[9]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[10]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[11]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[12]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[13]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[14]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[15]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[15]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[16]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[17]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[18]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[19]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[20]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[21]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[22]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[23]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[24]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[25]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[26]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[27]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[28]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[29]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[30]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[31]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[0]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[1]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[2]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[3]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[14]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[13]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[12]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[11]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[10]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[9]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[8]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[7]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[6]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[5]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[4]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[3]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[2]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[1]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[0]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[2]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[1]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[0]}]
+set_property IOSTANDARD DIFF_SSTL15_DCI [get_ports ddr3_ck_p[0]]
+set_property IOSTANDARD DIFF_SSTL15_DCI [get_ports ddr3_ck_n[0]]
+set_property IOSTANDARD SSTL15 [get_ports ddr3_ras_n]
+set_property IOSTANDARD SSTL15 [get_ports ddr3_cas_n]
+set_property IOSTANDARD SSTL15 [get_ports ddr3_we_n]
+set_property IOSTANDARD SSTL15 [get_ports ddr3_reset_n]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_cke[0]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_odt[0]}]
+# DDR3 CS not driven in this board 
+set_property IOSTANDARD SSTL15 [get_ports ddr3_cs_n*]
+set_property LOC AC12 [get_ports ddr3_cs_n*]
+
+set_property INTERNAL_VREF 0.75 [get_iobanks 34]
+set_property INTERNAL_VREF 0.90  [get_iobanks 33]
+
+set_property PACKAGE_PIN AF5 [get_ports ddr3_addr[0]]
+set_property PACKAGE_PIN AF2 [get_ports ddr3_addr[1]]
+set_property PACKAGE_PIN AD6 [get_ports ddr3_addr[2]]
+set_property PACKAGE_PIN AC6 [get_ports ddr3_addr[3]]
+set_property PACKAGE_PIN AD4 [get_ports ddr3_addr[4]]
+set_property PACKAGE_PIN AB6 [get_ports ddr3_addr[5]]
+set_property PACKAGE_PIN AE2 [get_ports ddr3_addr[6]]
+set_property PACKAGE_PIN Y5 [get_ports ddr3_addr[7]]
+set_property PACKAGE_PIN AA4 [get_ports ddr3_addr[8]]
+set_property PACKAGE_PIN AE6 [get_ports ddr3_addr[9]]
+set_property PACKAGE_PIN AE3 [get_ports ddr3_addr[10]]
+set_property PACKAGE_PIN AD5 [get_ports ddr3_addr[11]]
+set_property PACKAGE_PIN AB4 [get_ports ddr3_addr[12]]
+set_property PACKAGE_PIN Y6 [get_ports ddr3_addr[13]]
+
+set_property PACKAGE_PIN AD3 [get_ports ddr3_ba[0]]
+set_property PACKAGE_PIN AE1 [get_ports ddr3_ba[1]]
+set_property PACKAGE_PIN AE5 [get_ports ddr3_ba[2]]
+
+set_property PACKAGE_PIN AC4 [get_ports ddr3_cas_n]
+
+set_property PACKAGE_PIN AB5 [get_ports ddr3_ck_n[0]]
+set_property PACKAGE_PIN AA5 [get_ports ddr3_ck_p[0]]
+set_property PACKAGE_PIN AD1 [get_ports ddr3_cke[0]]
+set_property PACKAGE_PIN V1 [get_ports ddr3_dm[0]]
+set_property PACKAGE_PIN V3 [get_ports ddr3_dm[1]]
+set_property PACKAGE_PIN W1 [get_ports ddr3_dq[0]]
+set_property PACKAGE_PIN V2 [get_ports ddr3_dq[1]]
+set_property PACKAGE_PIN Y1 [get_ports ddr3_dq[2]]
+set_property PACKAGE_PIN Y3 [get_ports ddr3_dq[3]]
+set_property PACKAGE_PIN AC2 [get_ports ddr3_dq[4]]
+set_property PACKAGE_PIN Y2 [get_ports ddr3_dq[5]]
+set_property PACKAGE_PIN AB2 [get_ports ddr3_dq[6]]
+set_property PACKAGE_PIN AA3 [get_ports ddr3_dq[7]]
+set_property PACKAGE_PIN U1 [get_ports ddr3_dq[8]]
+set_property PACKAGE_PIN V4 [get_ports ddr3_dq[9]]
+set_property PACKAGE_PIN U6 [get_ports ddr3_dq[10]]
+set_property PACKAGE_PIN W3 [get_ports ddr3_dq[11]]
+set_property PACKAGE_PIN V6 [get_ports ddr3_dq[12]]
+set_property PACKAGE_PIN U2 [get_ports ddr3_dq[13]]
+set_property PACKAGE_PIN U7 [get_ports ddr3_dq[14]]
+set_property PACKAGE_PIN U5 [get_ports ddr3_dq[15]]
+
+set_property PACKAGE_PIN AF3 [get_ports ddr3_odt[0]]
+set_property PACKAGE_PIN AC3 [get_ports ddr3_ras_n]
+set_property W4 [get_ports ddr3_reset_n]
+set_property PACKAGE_PIN AF4 [get_ports ddr3_we_n]
+
+reset_property IOSTANDARD [get_ports {ddr3_dqs_*[*]}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[*]}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[*]}]
+set_property DIFF_TERM TRUE [get_ports {ddr3_dqs_p[*]}]
+set_property DIFF_TERM TRUE [get_ports {ddr3_dqs_n[*]}]
+set_property DIFF_PAIR ddr3_dqs_p[0] [get_ports {ddr3_dqs_n[0]}]
+set_property DIFF_PAIR ddr3_dqs_p[1] [get_ports {ddr3_dqs_n[1]}]
+set_property SLEW FAST [get_ports {ddr3_dqs_p[*] ddr3_dqs_n[*]}]
+set_property PACKAGE_PIN AC1 [get_ports {ddr3_dqs_n[0]}]
+set_property PACKAGE_PIN W5 [get_ports {ddr3_dqs_n[1]}]
+set_property PACKAGE_PIN AB1 [get_ports {ddr3_dqs_p[0]}]
+set_property PACKAGE_PIN W6 [get_ports {ddr3_dqs_p[1]}]
+
+
+set_max_delay -datapath_only -from [get_pins xlnx_ddr3_c0/u_xlnx_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/init_calib_complete_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 20.000

fpga/generator/Makefile

@@ -2,7 +2,7 @@ dst := IP
 
 all: ArtyA7
 
-.PHONY: ArtyA7 vcu118 vcu108 genesys2
+.PHONY: ArtyA7 vcu118 vcu108 genesys2 qmtechk7
 
 ArtyA7: export XILINX_PART := xc7a100tcsg324-1
 ArtyA7: export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1
@@ -32,13 +32,21 @@ genesys2: export SYSTEMCLOCK := 40000000
 genesys2: export MAXSDCCLOCK  := 10000000
 genesys2: FPGA_GENESYS2
 
+qmtechk7: export XILINX_PART := xc7k325tffg676-1
+# Not really a board from Xilinx
+qmtechk7: export XILINX_BOARD := qmtechk7
+qmtechk7: export board := qmtechk7
+qmtechk7: export SYSTEMCLOCK := 40000000
+qmtechk7: export MAXSDCCLOCK  := 10000000
+qmtechk7: FPGA_QMTECHK7
+
 # variables computed from config
 EXT_MEM_BASE = $(shell grep 'EXT_MEM_BASE' ../../config/deriv/fpga$(board)/config.vh | sed 's/.*=.*h\([[:alnum:]]*\);/0x\1/g')
 
 EXT_MEM_RANGE = $(shell grep 'EXT_MEM_RANGE' ../../config/deriv/fpga$(board)/config.vh | sed 's/.*=.*h\([[:alnum:]]*\);/\1/g' | sed 's/\(.*\)/base=16;\1+1/g' | bc | sed 's/\(.*\)/0x\1/g')
 
 
-.PHONY: FPGA_Arty FPGA_VCU
+.PHONY: FPGA_Arty FPGA_VCU FPGA_QMTECHK7
 FPGA_Arty: PreProcessFiles IP_Arty zsbl
 	vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
 FPGA_VCU: PreProcessFiles IP_VCU zsbl
@@ -47,8 +55,11 @@ FPGA_VCU: PreProcessFiles IP_VCU zsbl
 FPGA_GENESYS2: PreProcessFiles IP_GENESYS2 zsbl
 	vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
 
+FPGA_QMTECHK7: PreProcessFiles IP_QMTECHK7 zsbl
+	vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
+
 # Generate IP Blocks
-.PHONY: IP_Arty IP_VCU
+.PHONY: IP_Arty IP_VCU IP_QMTECHK7
 IP_VCU: $(dst)/sysrst.log \
 	MEM_VCU \
 	$(dst)/clkconverter.log \
@@ -65,8 +76,14 @@ IP_GENESYS2: $(dst)/sysrst.log \
 	$(dst)/clkconverter.log \
 	$(dst)/ahbaxibridge.log
 
+IP_QMTECHK7: $(dst)/sysrst.log \
+	MEM_QMTECHK7 \
+	$(dst)/mmcm-qmtechk7.log \
+	$(dst)/clkconverter.log \
+	$(dst)/ahbaxibridge.log
+
 # Generate Memory IP Blocks
-.PHONY: MEM_VCU MEM_Arty
+.PHONY: MEM_VCU MEM_Arty MEM_QMTECHK7
 MEM_VCU:
 	$(MAKE) $(dst)/ddr4-$(board).log
 MEM_Arty:
@@ -75,6 +92,9 @@ MEM_Arty:
 MEM_GENESYS2:
 	$(MAKE) $(dst)/ddr3-$(board).log
 
+MEM_QMTECHK7:
+	$(MAKE) $(dst)/ddr3-$(board).log
+
 # Copy files and make necessary modifications
 .PHONY: PreProcessFiles
 PreProcessFiles:

fpga/generator/ahbaxibridge.tcl

@@ -5,7 +5,7 @@ set boardName $::env(XILINX_BOARD)
 set ipName ahbaxibridge
 
 create_project $ipName . -force -part $partNumber
-if {$boardName!="ArtyA7"} {
+if {$boardName!="ArtyA7" && $boardName!="qmtechk7"} {
     set_property board_part $boardName [current_project]
 }
 

fpga/generator/clkconverter.tcl

@@ -7,7 +7,7 @@ set boardName $::env(XILINX_BOARD)
 set ipName clkconverter
 
 create_project $ipName . -force -part $partNumber
-if {$boardName!="ArtyA7"} {
+if {$boardName!="ArtyA7" && $boardName!="qmtechk7"} {
     set_property board_part $boardName [current_project]
 }
 

fpga/generator/ddr3-qmtechk7.tcl

@@ -0,0 +1,20 @@
+set partNumber $::env(XILINX_PART)
+set boardName $::env(XILINX_BOARD)
+
+set ipName ddr3
+
+create_project $ipName . -force -part $partNumber
+
+create_ip -name mig_7series -vendor xilinx.com -library ip -module_name $ipName
+
+exec mkdir -p IP/$ipName.srcs/sources_1/ip/$ipName
+exec cp ../xlnx_ddr3-qmtechk7-mig.prj $ipName.srcs/sources_1/ip/$ipName/xlnx_ddr3-qmtechk7-mig.prj
+
+set_property -dict [list CONFIG.XML_INPUT_FILE {xlnx_ddr3-qmtechk7-mig.prj} CONFIG.RESET_BOARD_INTERFACE {Custom} CONFIG.MIG_DONT_TOUCH_PARAM {Custom} CONFIG.BOARD_MIG_PARAM {Custom}] [get_ips $ipName]
+
+generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
+generate_target all [get_files  ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
+create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
+launch_run -jobs 8 ${ipName}_synth_1
+wait_on_run ${ipName}_synth_1
+